EVAL-AD5551/52EB Analog Devices Inc, EVAL-AD5551/52EB Datasheet - Page 8

• Manufacturer Part Number: EVAL-AD5551/52EB
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5551/52EB

• Lead Free Status / Rohs Status: Not Compliant

GENERAL DESCRIPTION
The AD5551/AD5552 are single, 14-bit, serial input, voltage
output DACs. They operate from a single supply ranging from
2.7 V to 5 V and consume typically 300 A with a supply of
5 V. Data is written to these devices in a 14-bit word format, via
a 3- or 4-wire serial interface. To ensure a known power-up state,
these parts were designed with a power-on reset function. In uni-
polar mode, the output is reset to 0 V, while in bipolar mode, the
AD5552 output is set to –V
the reference and analog ground are included on the AD5552.
Digital-to-Analog Section
The DAC architecture consists of two matched DAC sections.
A simplified circuit diagram is shown in Figure 2. The DAC
architecture of the AD5551/AD5552 is segmented. The four
MSBs of the 14-bit data word are decoded to drive 15 switches,
E1 to E15. Each of these switches connects one of 15 matched
resistors to either AGND or V
data word drive switches S0 to S9 of a 10-bit voltage mode
R-2R ladder network.
AD5551/AD5552
V
REF
2R
100
90
10
0%
100
90
10
0%
V
V
CLOCK (5V/DIV)
OUT
OUT
CS (5V/DIV)
10-BIT R-2R LADDER
2R
(0.1V/DIV)
2µs/DIV
S0
(50mV/DIV)
2 s/DIV
R
2R
S1
REF
REF
2R
S9
. Kelvin sense connections for
R
. The remaining 10 bits of the
FOUR MSBs DECODED INTO
15 EQUAL SEGMENTS
E1
2R
V
V
T
REF
DD
A
2R
V
V
T
E2
= 25 C
REF
DD
A
= 5V
= 25 C
= 2.5V
= 5V
= 2.5V
2R
E15
V
OUT
With this type of DAC configuration, the output impedance
is independent of code, while the input impedance seen by the ref-
erence is heavily code dependent. The output voltage is dependent
on the reference voltage as shown in the following equation.
where D is the decimal data word loaded to the DAC register
and N is the resolution of the DAC. For a reference of 2.5 V,
the equation simplifies to the following.
giving a V
full-scale loaded to the DAC.
The LSB size is V
Serial Interface
The AD5551 and AD5552 are controlled by a versatile 3-wire
serial interface, which operates at clock rates up to 25 MHz and
is compatible with SPI, QSPI, MICROWIRE, and DSP interface
standards. The timing diagram can be seen in Figure 1. Input
data is framed by the chip select input, CS. After a high-to-low
transition on CS, data is shifted synchronously and latched into
the input register on the rising edge of the serial clock, SCLK.
Data is loaded MSB first in 14-bit words. After 14 data bits
have been loaded into the serial input register, a low-to-high
transition on CS transfers the contents of the shift register to the
DAC. Data can only be loaded to the part while CS is low.
100
90
10
0%
100
90
10
0%
10pF
100pF
50pF
2µs/DIV
OUT
of 1.25 V with midscale loaded, and 2.5 V with
REF
/16,384.
V
V
T
V
REF
DD
A
V
OUT
= 25 C
OUT
= 5V
= 2.5V
200pF
=
V
V
T
=
A
REF
DD
V
16 384
= 25 C
2 5
REF
= 5V
.
= 2.5V
2
,
0.5 s/DIV
N
×
×
D
D
V
V
GAIN = –216
CS (5V/DIV)
V
OUT
OUT
OUT
(1V/DIV)
(50mV/DIV)
(0.5V/DIV)