M68EML08JLJK Freescale Semiconductor, M68EML08JLJK Datasheet - Page 16

• Manufacturer Part Number: M68EML08JLJK
• Manufacturer: Freescale Semiconductor

Specifications of M68EML08JLJK

• Lead Free Status / Rohs Status: Not Compliant

General Information
1.5 EML08JLJK Layout
M68EML08JLJK Emulation Module - Version 1.0
16
Figure 1-1 shows the layout of the EML08JLJK board. Board connectors and
configuration headers and switches are as follows:
Jumper header J4 specifies the clock signal source.
Dip switch SW1 specifies the MCU to be emulated.
Target interface connectors P4 and P5 connect the EML08JLJK to a target
system, via the included target cable assembly. If you use your EML08JLJK as
part of an MMDS, run the target cable assembly through the slit in the station
module enclosure.
Connector P1 connects to a logic analyzer.
DIN connectors P2 and P3, on the bottom of the board, connect the
EML08JLJK to the platform board.
The emulation MCU is at location U9.
The FPGA U24 is the logic control of the emulation modules on EML08JLJK.
Jumper headers J1 and J2 are for EM board design and factory use only.
P1
Figure 1-1 M68EML08JLJK Emulator Module
P2
General Information
U24
U9
J4
SW1
P3
P4
User’s Manual
MOTOROLA
P5