M68EML08JLJK Freescale Semiconductor, M68EML08JLJK Datasheet - Page 26
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M68EML08JLJK
Manufacturer Part Number
M68EML08JLJK
Description
Manufacturer
Freescale Semiconductor
Datasheet
1.M68EML08JLJK.pdf
(38 pages)
Specifications of M68EML08JLJK
Lead Free Status / Rohs Status
Not Compliant
Support Information
M68EML08JLJK Emulation Module - Version 1.0
26
Pin
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Table 3-1 Logic Analyzer Connector (P1) Signal Descriptions
Mnemonic
BREAK
RESET
LBOX
GND
GND
GND
GND
GND
GND
GND
V
LA2
LA1
LA0
DD
Support Information
Last bus cycle — Input signal that the emulator asserts to
indicate that the target system MCU is in the last bus cycle of
an instruction
Address bus bit 2 — MCU output address bus
Active low signal that the EM asserts to stop the target system
MCU from running user code
Address bus bit 1 — MCU output address bus
GROUND
Address bus bit 0 — MCU output address bus
GROUND
GROUND
GROUND
GROUND
GROUND
Active-low bidirectional signal for starting an EVS reset
Input voltage (+5 Vdc @ 1A (max)) used by the EM logic
circuits
GROUND
Signal Description
User’s Manual
MOTOROLA