SRI4K-A3T/1GE STMicroelectronics, SRI4K-A3T/1GE Datasheet - Page 4

• Manufacturer Part Number: SRI4K-A3T/1GE
• Manufacturer: STMicroelectronics

Specifications of SRI4K-A3T/1GE

• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

SRI4K
SUMMARY DESCRIPTION
The SRI4K is a contactless memory, powered by
an externally transmitted radio wave. It contains a
4096-bit user EEPROM fabricated with STMicro-
electronics CMOS technology. The memory is or-
ganized as 128 blocks of 32 bits. The SRI4K is
accessed via the 13.56MHz carrier. Incoming data
are demodulated and decoded from the received
Amplitude Shift Keying (ASK) modulation signal
and outgoing data are generated by load variation
using Bit Phase Shift Keying (BPSK) coding of a
847kHz sub-carrier. The received ASK wave is
10% modulated. The Data transfer rate between
the SRI4K and the reader is 106kbit/s in both re-
ception and emission modes.
The SRI4K follows the ISO 14443 part 2 type B
recommendation for the radio-frequency power
and signal interface.
Figure 2. Logic Diagram
The SRI4K is specifically designed for short range
applications that need re-usable products. The
SRI4K includes an anti-collision mechanism that
allows it to detect and select tags present at the
same time within range of the reader. The anti-col-
lision is based on a probabilistic scanning method
using slot markers. Using the STMicroelectronics
single chip coupler, CRX14, it is easy to design a
reader and build a contactless system.
Table 1. Signal Names
4/41
AC1
AC0
EEPROM
4 Kbit
User
SRI4K
Demodulator
Antenna Coil
Antenna Coil
Modulator
Regulator
Supply
Power
BPSK
Load
ASK
AI10878
AC0
AC1
The SRI4K contactless EEPROM can be random-
ly read and written in block mode (each block con-
taining 32 bits). The instruction set includes the
following nine commands:
The SRI4K memory is organized in three areas, as
described in
ble OTP (one time programmable) area in which
bits can only be switched from 1 to 0. Using a spe-
cial command, it is possible to erase all bits of this
area to 1. The second area provides two 32-bit bi-
nary counters which can only be decremented
from FFFFFFFFh to 00000000h, and gives a ca-
pacity of 4,294,967,296 units per counter. The last
area is the EEPROM memory. It is accessible by
block of 32 bits and includes an auto-erase cycle
during each WRITE_BLOCK command.
Figure 3. Die Floor Plan
SIGNAL DESCRIPTION
AC1, AC0. The pads for the Antenna Coil. AC1
and AC0 must be directly bonded to the antenna.
READ_BLOCK
WRITE_BLOCK
INITIATE
PCALL16
SLOT_MARKER
SELECT
COMPLETION
RESET_TO_INVENTORY
GET_UID
AC0
Figure
13.. The first area is a resetta-
AC1
AI09055