COM20022I-HT Standard Microsystems (SMSC), COM20022I-HT Datasheet - Page 70

• Manufacturer Part Number: COM20022I-HT
• Manufacturer: Standard Microsystems (SMSC)

Specifications of COM20022I-HT

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Compliant

Revision 09-27-07
nIOCS16
D0-D15
A0-A2
nCS
nDS
*
**** t12 is measured from the latest active (valid) timing among nCS, A0-A2.
*****
Note 1:
**Note 2: Any cycle occurring after a write to the Address Pointer Low Register
Note 2 is applied to an access to Data Register by DMA transfer.
DIR
t10
t11
t12
t13
T
T
T
T
t1
t2
t3
t4
t5
t6
t7
t8
t9
Figure 8.12 - Non-Multiplexed Bus, 68XX-Like Control Signals; Write Cycle
opr
ARB
ARB
ARB
t13 is measured from the earliest inactive (invalid) timing among nCS, A0-A2.
is the period of operation clock. It depends on CKUP1 and CKUP0 bits
is the Arbitration Clock Period
is identical to T
is twice T
Address Setup to nDS Active
Address Hold from nDS Inactive
nCS Setup to nDS Active
nCS Hold from nDS Inactive
DIR Setup to nDS Active
Cycle Time (nDS
DIR Hold from nDS Inactive
Valid Data Setup to nDS High
Data Hold from nDS High
nDS Low Width
nDS High Width
nIOCS16 Output Delay from nCS Low
nIOCS16 Hold Delay from nCS High
Write cycle for Address Pointer Low Register occurring after an access to
Data Register requires a minimum of 5T
the leading edge of the next nDS.
requires a minimum of 4T
of the next nDS.
The Microcontroller typically accesses the COM20022 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20022 cycles.
opr
if SLOW ARB = 1
Parameter
opr
t1
if SLOW ARB = 0
to Next
CASE 2: BUSTMG pin = LOW
t5
t3
DATASHEET
t12
ARB
from the trailing edge of nDS to the leading edge
)**
VALID
Page 70
ARB
t10
from the trailing edge of nDS to
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
VALID DATA
VALID VALUE
4T
t8
min
0*****
10
10
30
10
65
30
ARB
0
0
0
0
*
40****
max
t9
t2
t7
Note 2
t4
t11
t6**
units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
t13
t6
SMSC COM20022I
Datasheet