IS42S16100F-7BLI ISSI, Integrated Silicon Solution Inc, IS42S16100F-7BLI Datasheet - Page 22

• Manufacturer Part Number: IS42S16100F-7BLI
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS42S16100F-7BLI

• Lead Free Status / Rohs Status: Compliant

IS42/45S16100F, IS42VS16100F
OPERATION COMMAND TABLE
Current State Command
Notes:
1. H: HIGH level input, L: LOW level input, X: "Don't Care" input, V: Valid data input
2. All input signals are latched on the rising edge of the CLK signal.
3. Both banks must be placed in the inactive (idle) state in advance.
4. The state of the A0 to A11 pins is loaded into the mode register as an OP code.
5. The row address is generated automatically internally at this time. The DQ pin and the address pin data is ignored.
6. During a self-refresh operation, all pin data (states) other than CKe is ignored.
7. The selected bank must be placed in the inactive (idle) state in advance.
8. The selected bank must be placed in the active state in advance.
9. This command is valid only when the burst length set to full page.
10. This is possible depending on the state of the bank selected by the A11 pin.
11. Time to switch internal busses is required.
12. The SDRAM can be switched to power-down mode by dropping the CKe pin LOW when both banks in the idle state. Input pins
other than CKE are ignored at this time.
13. The SDRAM can be switched to self-refresh mode by dropping the CKe pin LOW when both banks in the idle state. Input pins
other than CKE are ignored at this time.
14. Possible if t
15. Illegal if t
16. The conditions for burst interruption must be observed. Also note that the SDRAM will enter the pre
state immediately after the burst operation completes if auto-precharge is selected.
17. Command input becomes possible after the period t
immediately after the burst operation completes if auto-precharge is selected.
18. A8,A9 = don’t care.
22
Write Recovery
With Auto-
Precharge
Refresh
Mode Register DeSL
Set
ras
rrd
is not satisfied.
DeSL
NOP
BST
ReAD/ReADA
WRIT/WRITA
ACT
PRe/PALL
ReF/SeLF
MRS
DeSL
NOP
BST
ReAD/ReADA
WRIT/WRITA
ACT
PRe/PALL
ReF/SeLF
MRS
NOP
BST
ReAD/ReADA
WRIT/WRITA
ACT
PRe/PALL
ReF/SeLF
MRS
is satisfied.
Operation
No Operation, Idle State After t
No Operation, Idle State After t
No Operation, Idle State After t
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
No Operation, Idle State After t
No Operation, Idle State After t
No Operation, Idle State After t
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
No Operation, Idle State After t
No Operation, Idle State After t
No Operation, Idle State After t
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
(10)
(10)
(10)
(10)
(1,2)
rcd
has elapsed. Also note that the SDRAM will enter the precharged state
dal
dal
dal
rp
rp
rp
mcd
mcd
mcd
Has elapsed
Has elapsed
Has elapsed
Has elapsed
Has elapsed
Has elapsed
Has elapsed
Has elapsed
Has elapsed
Integrated Silicon Solution, Inc. — www.issi.com
CS RAS CAS WE A11 A10 A9-A0
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
X
L
L
L
L
X
L
L
L
L
X
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
X
L
L
L
L
X
L
L
L
L
X
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
X
L
X
L
X
L
L
L
L
L
L
L
L
L
L
X
X
X
V
V
V
V
X
X
X
X
V
V
V
V
X
X
X
X
V
V
V
V
X
OP CODe
OP CODe
OP CODe
charged
X
X
X
V
V
V
V
X
X
X
X
V
V
V
V
X
X
X
X
V
V
V
V
X
06/03/2010
Rev. 00C
V
V
V
V
V
V
V
V
V
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(18)
(18)
(18)
(18)
(18)
(18)
(18)
(18)
(18)