IS42S16100F-7BLI ISSI, Integrated Silicon Solution Inc, IS42S16100F-7BLI Datasheet - Page 37

• Manufacturer Part Number: IS42S16100F-7BLI
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS42S16100F-7BLI

• Lead Free Status / Rohs Status: Compliant

IS42/45S16100F, IS42VS16100F
Write Cycle Interruption Using the
Precharge Command
A write cycle can be interrupted by the execution of the
precharge command before that cycle completes. The
delay time (t
where burst input is invalid, i.e., the point where input data
is no longer written to device internal memory is zero clock
cycles regardless of the CAS.
To inhibit invalid write, the DQM signal must be asserted
HIGH with the precharge command.
This precharge command and burst write command must
be of the same bank, otherwise it is not precharge interrupt
but only another bank precharge of dual bank operation.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
06/03/2010
CAS latency = 2, burstlength = 4
CAS latency = 3, burstlength = 4
COMMAND
COMMAND
wdl
) from the precharge command to the point
CLK
DQ
DQM
CLK
DQ
WRITE (CA=A, BANK 0)
WRITE A0
D
WRITE (CA=A, BANK 0)
IN
A0 D
WRITE A0
D
IN
IN
A0
A1 D
D
IN
A1
IN
A2
D
IN
D
IN
A2
t
A3
DPL
Inversely, to write all the burst data to the device, the
precharge command must be executed after the write
data recovery period (t
precharge command must be executed two clock cycles
after the input of the last burst data item.
PRECHARGE (BANK 0)
D
PRE 0
CAS Latency
IN
A3
t
MASKED BY DQM
t
wdl
PRECHARGE (BANK 0)
dpl
t
WDL
PRE 0
=0
dpl
) has elapsed. Therefore, the
3
0
2
2
0
2
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