IS42S16100F-7BLI ISSI, Integrated Silicon Solution Inc, IS42S16100F-7BLI Datasheet - Page 40

• Manufacturer Part Number: IS42S16100F-7BLI
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS42S16100F-7BLI

• Lead Free Status / Rohs Status: Compliant

IS42/45S16100F, IS42VS16100F
Burst Data Interruption U/LDQM Pins (Write
Cycle)
Burst data input can be temporarily interrupted (muted )
during a write cycle using the U/LDQM pins. Regardless
of the CAS latency, as soon as one of the U/LDQM pins
goes HIGH, the corresponding externally applied input
data will no longer be written to the device internal circuits.
Subsequently, the corresponding input continues to be
muted as long as that U/LDQM pin remains HIGH.
The SDRAM will revert to accepting input as soon as
40
Burst Read and Single Write
The burst read and single write mode is set up using the
mode register set command. During this operation, the burst
read cycle operates normally, but the write cycle only writes
a single data item for each write cycle. The CAS latency
and DQM latency are the same as in normal mode.
CAS latency = 2, burstlength = 4
CAS latency = 2, 3
COMMAND
COMMAND
DQ8-DQ15
DQ0-DQ7
UDQM
LDQM
CLK
CLK
DQ
WRITE (CA=A, BANK 0)
DATA MASK (UPPER BYTE)
WRITE (CA=A, BANK 0)
DATA MASK (LOWER BYTE)
WRITE A0
WRITE A0
D
D
t
IN
DMD=0
IN
A0
A0
D
IN
that pin is dropped to LOW and data will be written to the
device. This input control operates independently on a byte
basis with the UDQM pin controlling upper byte input (pin
DQ8 to DQ15) and the LDQM pin controlling the lower
byte input (pins DQ0 to DQ7).
Since the U/LDQM pins control the device input buffers
only, the cycle continues internally and, in particular,
incrementing of the internal burst counter continues.
A1
Integrated Silicon Solution, Inc. — www.issi.com
D
IN
A2
D
D
IN
IN
A3
A3
Don't Care
06/03/2010
Rev. 00C