K4H511638C-ZCB3 Samsung Semiconductor, K4H511638C-ZCB3 Datasheet - Page 19
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K4H511638C-ZCB3
Manufacturer Part Number
K4H511638C-ZCB3
Description
Manufacturer
Samsung Semiconductor
Type
DDR SDRAMr
Datasheet
1.K4H511638C-ZCB3.pdf
(24 pages)
Specifications of K4H511638C-ZCB3
Organization
32Mx16
Density
512Mb
Address Bus
15b
Access Time (max)
700ps
Maximum Clock Rate
333MHz
Operating Supply Voltage (typ)
2.5V
Package Type
FBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Supply Current
185mA
Pin Count
60
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
K4H511638C-ZCB3
Manufacturer:
SAMSUNG
Quantity:
13
DDR SDRAM 512Mb C-die (x4, x8, x16)
Component Notes
17. For CK & CK slew rate ≥ 1.0 V/ns
18. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by
19. Slew Rate is measured between VOH(ac) and VOL(ac).
20. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
21. tQH = tHP - tQHS, where:
22. tDQSQ
23. tDAL = (tWR/tCK) + (tRP/tCK)
device design or tester correlation.
Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle.
value can be greater than the minimum specification limits for tCL and tCH).....For example, tCL and tCH are = 50% of the
period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into
the clock traces.
case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-
channel to n-channel variation of the output drivers.
For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR266B at CL=2.5 and
tCK=7.5ns tDAL = (15 ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3)
tDAL = 5 clocks
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The
pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one tansition followed by the worst
Rev. 1.1 June. 2005
DDR SDRAM