IS42S16800A7TLTR ISSI, Integrated Silicon Solution Inc, IS42S16800A7TLTR Datasheet - Page 10

• Manufacturer Part Number: IS42S16800A7TLTR
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS42S16800A7TLTR

• Organization: 8Mx16
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 143MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 150mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

IS42S16800A
10
FUNCTIONAL TRUTH TABLE Continued:
Write Recovering
Write Recovering
with Auto
Precharge
Refresh
Mode Register
Accessing
Note: H=V
IH
, L=V
IL
x= V
CS
CS
CS
CS
CS
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
IH
or V
H
H
H
H
L
L
L
L
×
H
H
H
H
L
L
L
L
×
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
×
×
RAS
RAS
RAS CAS
RAS
RAS
IL
, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code
CAS
CAS
CAS
H
H
L
L
H
H
L
L
×
H
H
L
L
H
H
L
L
×
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
CAS
×
×
×
H
L
H
L
H
L
H
L
×
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
×
H
L
H
L
H
L
H
L
×
WE
WE
WE
WE
WE
Address
×
×
×
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
×
OC, BA
×
×
×
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
OC, BA
×
×
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
×
OC, BA
×
×
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
×
OC, BA
×
×
×
Integrated Silicon Solution, Inc. — www.issi.com
Command
DESL
NOP
BST
READ/READA
WRIT/ WRITA
ACT
PRE/PALL
REF
MRS
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF
MRS
DESL
NOP
BST
EAD/READA
WRIT/WRITA
ACT
PRE/PALL
REF
MRS
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF
MRS
Action
Nop Enter row active after tDPL
Nop Enter row active after tDPL
Nop Enter row active after tDPL
Begin read
Begin new write
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Nop Enter precharge after tDPL
Nop Enter precharge after tDPL
Nop Enter row active after tDPL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Enter idle after tRC1
Nop Enter idle after tRC1
Nop Enter idle after tRC1
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Nop Enter idle after tRSC
Nop Enter idle after tRSC
Nop Enter idle after tRSC
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
(2)
(2)
(2, 6)
(2)
(2)
(6)
06/01/07
Rev. A