IS42S16800A7TLTR ISSI, Integrated Silicon Solution Inc, IS42S16800A7TLTR Datasheet - Page 25

• Manufacturer Part Number: IS42S16800A7TLTR
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS42S16800A7TLTR

• Organization: 8Mx16
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 143MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 150mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

IS42S16800A
CHIP OPERATION
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be issued to a
bank within the SDRAM, a row in that bank must be “opened.”
This is accomplished via the ACTIVE command, which
selects both the bank and the row to be activated (see
Activating Specific Row Within Specific Bank).
After opening a row (issuing an ACTIVE command), a
READ or WRITE command may be issued to that row,
subject to the t
divided by the clock period and rounded up to the next whole
number to determine the earliest clock edge after the
ACTIVE command on which a READ or WRITE command
can be entered. For example, a t
with a 125 MHz clock (8ns period) results in 2.5 clocks,
rounded to 3. This is reflected in the following example,
which covers any case where 2 < [t
same procedure is used to convert other specification limits
from time units to clock cycles).
A subsequent ACTIVE command to a different row in the
same bank can only be issued after the previous active row
has been “closed” (precharged). The minimum time interval
between successive ACTIVE commands to the same bank
is defined by t
A subsequent ACTIVE command to another bank can be
issued while the first bank is being accessed, which results
in a reduction of total row-access overhead. The minimum
time interval between successive ACTIVE commands to
different banks is defined by t
EXAMPLE: MEETING TRCD (MIN) WHEN 2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/01/07
RC
RCD
.
specification. Minimum t
COMMAND
RRD
CLK
RCD
.
RCD
specification of 20ns
(MIN)/t
ACTIVE
T0
RCD
CK
should be
] 3. (The
t
NOP
RCD
T1
[TRCD (MIN)/TCK]
ACTIVATING SPECIFIC ROW WITHIN SPE-
CIFIC BANK
BA0, BA1
A0-A11
NOP
T2
CKE
RAS
CAS
CLK
WE
CS
HIGH
READ or
WRITE
T3
DON'T CARE
3
BANK ADDRESS
ROW ADDRESS
T4
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