IS42S16800A7TLTR ISSI, Integrated Silicon Solution Inc, IS42S16800A7TLTR Datasheet - Page 27

• Manufacturer Part Number: IS42S16800A7TLTR
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS42S16800A7TLTR

• Organization: 8Mx16
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 143MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 150mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

IS42S16800A
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/01/07
same bank. The PRECHARGE command should be is-
sued x cycles before the clock edge at which the last desired
data element is valid, where x equals the CAS latency minus
one. This is shown in the READ to PRECHARGE diagram for
each possible CAS latency; data element n + 3 is either the
last of a burst of four or the last desired of a longer burst.
Following the PRECHARGE command, a subsequent com-
mand to the same bank cannot be issued until t
that part of the row precharge time is hidden during the
access of the last data element(s).
In the case of a fixed-length burst being executed to comple-
tion, a PRECHARGE command issued at the optimum time
(as described above) provides the same operation that
would result from the same fixed-length burst with auto
precharge. The disadvantage of the PRECHARGE com-
mand is that it requires that the command and address
buses be available at the appropriate time to issue the
command; the advantage of the PRECHARGE command is
that it can be used to truncate fixed-length or full-page
bursts.
Full-page READ bursts can be truncated with the BURST
TERMINATE command, and fixed-length READ bursts
may be truncated with a BURST TERMINATE command,
provided that auto precharge was not activated. The BURST
TERMINATE command should be issued x cycles before
the clock edge at which the last desired data element is
valid, where x equals the CAS latency minus one. This is
shown in the READ Burst Termination diagram for each
possible CAS latency; data element n + 3 is the last desired
data element of a longer burst.
RP
is met. Note
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