MT45W256KW16BEGB-708 WT Micron Technology Inc, MT45W256KW16BEGB-708 WT Datasheet
MT45W256KW16BEGB-708 WT
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MT45W256KW16BEGB-708 WT Summary of contents
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... Designator 1 2 ature exceed the CellularRAM Workgroup 1.0 specification. 2. Contact factory for availability. Part Number Example: MT45W256KW16BEGB-701WT Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. Features 6 CRE DQ0 DQ2 ...
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Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1: 54-Ball VFBGA Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 1: VFBGA Ball Descriptions ...
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... General Description Micron power, portable applications. The MT45W256KW16BEGB is a 4Mb DRAM core device organized as 256K x 16 bits. This device includes an industry-standard burst mode Flash interface that dramatically increases read/write bandwidth compared with other low-power SRAM or pseudo-SRAM (PSRAM) offerings. For seamless operation on a burst Flash bus, CellularRAM products incorporate a trans- parent self refresh mechanism ...
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Ball Descriptions Table 1: VFBGA Ball Descriptions VFBGA Assignment Symbol Type D3, E4, F4, F3, A[17:0] Input G4, G3, H5, H4, H3, H2, D4, C4, C3, B4, B3, A5, A4 CLK Input J3 ADV# Input A6 CRE Input ...
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Bus Operations Table 2: Bus Operations: Asynchronous Mode Mode Power CLK READ Active WRITE Active Standby Standby Idle No operation Configuration Active register WRITE Configuration Active register READ DPD Deep power-down Notes: 1. CLK must be static HIGH or LOW ...
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Table 3: Bus Operations: Burst Mode Mode Power CLK Active Asynchronous READ Active Asynchronous WRITE Standby Standby No operation Idle Active Initial burst READ Active Initial burst WRITE Active Burst continue Active Burst suspend Active Configuration register WRITE Active Configuration ...
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Part Numbering Information Micron CellularRAM devices are available in several different configurations and densi- ties (see Figure 3). Figure 3: Part Number Chart 256K W 16 Micron Technology Product Family 45 = PSRAM/CellularRAM memory Operating Core Voltage ...
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... Functional Description In general, MT45W256KW16BEGB devices are high-density alternatives to SRAM and PSRAM products, popular in low-power, portable applications. The MT45W256KW16BEGB contains a 4,194,304-bit DRAM core organized as 262,144 addresses by 16 bits. This device implements the same high-speed bus interface found on burst mode Flash products. The CellularRAM bus interface supports both asynchronous and burst mode transfers. ...
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Figure 5: READ Operation (ADV = LOW) CE# OE# WE# Address Data LB#/UB# Note: ADV must remain LOW for page mode operation. Figure 6: WRITE Operation (ADV = LOW) CE# OE# WE# Address Data LB#/UB# PDF: 09005aef8329f3e3 / Source: 09005aef82e419a5 ...
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Page Mode READ Operation Page mode is a performance-enhancing extension to the legacy asynchronous READ operation. In page-mode-capable products, an initial asynchronous READ access is performed, and then adjacent addresses can be read quickly by simply changing the low-order address. ...
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The WAIT output will be asserted as soon as CE# goes LOW and will be deasserted to indicate when data transferred into or out of the memory. WAIT will again be asserted if the burst crosses the ...
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Figure 9: Burst Mode WRITE (4-Word Burst) CLK A[17:0] ADV# CE# OE# WE# WAIT DQ[15:0] LB#/UB# WRITE burst Identified (WE# = LOW) Note: Nondefault BCR settings: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. Mixed-Mode Operation ...
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WAIT Operation The WAIT output on a CellularRAM device is typically connected to a shared, system- level WAIT signal (see Figure 10). The shared WAIT signal is used by the processor to coordinate transactions with multiple memories on the synchronous ...
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Figure 11: Refresh Collision During READ Operation V IH CLK A[17:0] Valid V address ADV ...
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Low-Power Operation Standby Mode Operation During standby, the device current consumption is reduced to the level necessary to perform the DRAM REFRESH operation. Standby operation occurs when CE# is HIGH. The device will enter a reduced power state upon completion ...
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Configuration Registers Two user-accessible configuration registers define the device operation. The bus config- uration register (BCR) defines how the CellularRAM interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh ...
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Figure 14: Synchronous Mode Configuration Register WRITE Followed by READ ARRAY Operation CLK Latch control register value A[16:0] OPCODE A[17 CRE ADV CSP CE# OE# t ...
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Figure 15: Asynchronous Mode Configuration Register READ Followed by READ ARRAY Operation A[16:0] t AVS Select register 1 A[17] CRE t VPH ADV# CE# Initiate register access OE# WE# LB#/UB# DQ[15:0] Notes: 1. A[17] = LOW to load RCR; A[17] ...
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Figure 16: Synchronous Mode Configuration Register READ Followed by READ ARRAY Operation CLK Latch control register value A[16: A[17 CRE ADV CSP CE# OE# WE# t ...
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Software Access to the Configuration Register Software access of the configuration registers uses a sequence of asynchronous READ and asynchronous WRITE operations. The contents of the configuration registers can be read or modified using the software sequence. The configuration registers ...
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Figure 18: Read Configuration Register Address CE# OE# WE# LB#/UB# Data Notes possible that the data stored at the highest memory location will be altered if the data at the falling edge of WE# is not 0000h ...
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Bus Configuration Register The BCR defines how the CellularRAM device interacts with the system memory bus. Page mode operation is enabled by a bit contained in the RCR. Figure 19 defines the control bits in the BCR. At power-up, the ...
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Table 4: Sequence and Burst Length 4-Word Starting Burst Burst Wrap Address Length BCR[3] Wrap (Decimal) Linear 0 Yes 0 0-1-2-3 1 1-2-3-0 2 2-3-0-1 3 3-0-1 ... 0-1-2-3 1 1-2-3-4 ...
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Output Impedance (BCR[5]) Default = Outputs Use Full-Drive Strength The output driver strength can be altered to adjust for different data bus loading scenarios. The reduced-strength option should be more than adequate in stacked chip (Flash + CellularRAM) environments when ...
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Figure 22: WAIT Configuration During Burst Operation CLK WAIT WAIT DQ[15:0] Note: Nondefault BCR setting for WAIT during BURST operation: WAIT active LOW. WAIT Polarity (BCR[10]) Default = WAIT Active HIGH The WAIT polarity bit indicates whether an asserted WAIT ...
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Refresh Configuration Register The refresh configuration register (RCR) defines how the CellularRAM device performs its transparent self refresh. Altering the refresh parameters can dramatically reduce current consumption during standby mode. Page mode control is also embedded into the RCR. Figure ...
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Electrical Characteristics Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of ...
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Table 7: Electrical Characteristics and Operating Conditions Wireless temperature Description Supply voltage I/O supply voltage Input high voltage Input low voltage Output high voltage Output low voltage Input leakage current Output leakage current Operating Current Asynchronous random READ/ WRITE Asynchronous ...
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Typical Standby Currents The following figure refers to typical standby currents for the device. Figure 25: Typical Refresh Current vs. Temperature –45 –35 –25 –15 –5 Note: Typical I PDF: 09005aef8329f3e3 / ...
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Table 8: Deep Power-Down Specifications Description Deep power-down Table 9: Capacitance Description Input capacitance Input/output capacitance (DQ) Notes: 1. These parameters are verified in device characterization and are not 100% tested. Figure 26: AC Input/Output Reference Waveform ...
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Timing Requirements Table 10: Asynchronous READ Cycle Timing Requirements 1 Parameter Address access time ADV# access time Page access time Address hold from ADV# HIGH Address setup to ADV# HIGH LB#/UB# access time LB#/UB# disable to DQ High-Z output LB#/UB# ...
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Table 11: Burst READ Cycle Timing Requirements 1 Parameter Burst to READ access time CLK to output delay Burst OE# LOW to output delay CE# HIGH between subsequent burst and mixed-mode operations Maximum CE# pulse width CE# LOW to WAIT ...
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Table 12: Asynchronous WRITE Cycle Timing Requirements Parameter Address and ADV# LOW setup time Address hold from ADV# going HIGH Address setup to ADV# going HIGH Address valid to end of WRITE LB#/UB# select to end of WRITE CE# LOW ...
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Table 13: Burst WRITE Cycle Timing Requirements Parameter CE# HIGH between subsequent burst and mixed-mode operations Minimum CE# pulse width CE# LOW to WAIT valid Clock period CE# setup to CLK active edge Hold time from active CLK edge Chip ...
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Timing Diagrams Figure 29: Asynchronous READ A[17:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] WAIT PDF: 09005aef8329f3e3 / Source: 09005aef82e419a5 8mb_4mb_burst_cr1_0_p22z__2.fm - Rev 4Mb: 256K x 16 Async/Page/Burst CellularRAM 1.0 Memory Valid address ...
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Figure 30: Asynchronous READ Using ADV# A[17:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] WAIT PDF: 09005aef8329f3e3 / Source: 09005aef82e419a5 8mb_4mb_burst_cr1_0_p22z__2.fm - Rev 4Mb: 256K x 16 Async/Page/Burst CellularRAM 1.0 Memory V IH Valid address V IL ...
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Figure 31: Page Mode READ A[17:4] A[3:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] WAIT PDF: 09005aef8329f3e3 / Source: 09005aef82e419a5 8mb_4mb_burst_cr1_0_p22z__2.fm - Rev 4Mb: 256K x 16 Async/Page/Burst CellularRAM 1.0 Memory Valid address ...
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Figure 32: Single-Access Burst READ Operation V IH CLK A[17:0] Valid address ADV CSP ...
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Figure 33: Four-Word Burst READ Operation V IH CLK A[17:0] Valid address ADV CSP ...
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Figure 34: READ Burst Suspend V IH CLK Valid A[17:0] V address ADV CSP OE# ...
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Figure 35: Output Delay in Continuous Burst READ with BCR[ for End-of-Row Condition V IH CLK CLK V IH A[17: ADV LB#/UB CE# ...
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Figure 36: CE#-Controlled Asynchronous WRITE A[17:0] ADV# LB#/UB# OE# WE# DQ[15:0] DQ[15:0] OUT WAIT PDF: 09005aef8329f3e3 / Source: 09005aef82e419a5 8mb_4mb_burst_cr1_0_p22z__2.fm - Rev 4Mb: 256K x 16 Async/Page/Burst CellularRAM 1.0 Memory Valid address ...
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Figure 37: LB#/UB#-Controlled Asynchronous WRITE A[17:0] ADV# LB#/UB# OE# WE# DQ[15:0] DQ[15:0] OUT WAIT PDF: 09005aef8329f3e3 / Source: 09005aef82e419a5 8mb_4mb_burst_cr1_0_p22z__2.fm - Rev 4Mb: 256K x 16 Async/Page/Burst CellularRAM 1.0 Memory Valid address ...
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Figure 38: WE#-Controlled Asynchronous WRITE A[17:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] DQ[15:0] OUT WAIT PDF: 09005aef8329f3e3 / Source: 09005aef82e419a5 8mb_4mb_burst_cr1_0_p22z__2.fm - Rev 4Mb: 256K x 16 Async/Page/Burst CellularRAM 1.0 Memory V IH Valid address V ...
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Figure 39: Asynchronous WRITE Using ADV# A[17:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] DQ[15:0] OUT WAIT PDF: 09005aef8329f3e3 / Source: 09005aef82e419a5 8mb_4mb_burst_cr1_0_p22z__2.fm - Rev 4Mb: 256K x 16 Async/Page/Burst CellularRAM 1.0 Memory V IH Valid address ...
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Figure 40: Burst WRITE Operation V IH CLK A[17:0] Valid address ADV LB#/UB CSP V IH CE# ...
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Figure 41: Output Delay in Continuous Burst Write with BCR[ for End-of-Row Condition V IH CLK CLK V IH A[17: ADV LB#/UB CE# ...
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Figure 42: Burst WRITE Followed by Burst READ t CLK V IH CLK A[17:0] Valid address ADV LB#/UB ...
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Figure 43: Asynchronous WRITE Followed by Burst READ V IH CLK Valid Valid A[17:0] address address AVS t AVH VPH V IH ADV ...
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Figure 44: Asynchronous WRITE Followed by Burst READ with ADV# LOW V IH CLK A[17:0] Valid Valid address address AVS t AVH VPH V IH ADV# ...
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Figure 45: Burst READ Followed by Asynchronous WRITE (WE#-Controlled CLK A[17:0] Valid address ADV CSP V IH CE# V ...
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Figure 46: Burst READ Followed by Asynchronous WRITE Using ADV CLK A[17:0] Valid address ADV CSP ...
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Figure 47: Asynchronous WRITE Followed by Asynchronous READ – ADV# LOW V IH A[17:0] Valid address ADV LB#/ ...
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Figure 48: Asynchronous WRITE Followed by Asynchronous READ V IH A[17:0] Valid address VPH V IH ADV LB#/ WE# ...
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... All dimensions are in millimeters; MAX/MIN or typical (TYP) where noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 3. The MT45W256KW16BEGB uses “green” packaging. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc ...
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Revision History Rev. B, Production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...