MT45W256KW16BEGB-708 WT Micron Technology Inc, MT45W256KW16BEGB-708 WT Datasheet - Page 27

• Manufacturer Part Number: MT45W256KW16BEGB-708 WT
• Manufacturer: Micron Technology Inc

Specifications of MT45W256KW16BEGB-708 WT

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Figure 22:
WAIT Polarity (BCR[10]) Default = WAIT Active HIGH
Latency Counter (BCR[13:11]) Default = Three-Clock Latency
Operating Mode (BCR[15]) Default = Asynchronous Operation
Table 5:
Figure 23:
PDF: 09005aef8329f3e3 / Source: 09005aef82e419a5
8mb_4mb_burst_cr1_0_p22z__2.fm - Rev. B 4/ 08 EN
Latency Configuration Code
2 (3 clocks)
3 (4 clocks) – default
DQ[15:0]
DQ[15:0]
DQ[15:0]
WAIT
WAIT
A[17:0]
ADV#
CLK
CLK
Latency Configuration
V
V
V
V
V
V
V
V
V
V
WAIT Configuration During Burst Operation
Latency Counter (Variable Latency, No Refresh Collision)
IH
IL
IH
IL
IH
IL
OH
OL
OH
OL
Note:
address
Valid
The WAIT polarity bit indicates whether an asserted WAIT output should be HIGH or
LOW. This bit will determine whether the WAIT signal requires a pull-up or pull-down
resistor to maintain the deasserted state.
The latency counter bits determine how many clocks occur between the beginning of a
READ or WRITE operation and the first data value transferred. Only latency code 2
(3 clocks) or latency code 3 (4 clocks) is allowed (see Table 5 and Figure 23).
The operating mode bit either selects synchronous BURST operation or the default
asynchronous mode of operation.
Nondefault BCR setting for WAIT during BURST operation: WAIT active LOW.
Code 2
Code 3
D[0]
4Mb: 256K x 16 Async/Page/Burst CellularRAM 1.0 Memory
(Default)
D[1]
27
output
Valid
104 (9.62ns)
104 MHz
66 (15ns)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D[2]
output
output
Valid
Valid
Max Input CLK Frequency
D[3]
output
output
Valid
Valid
Configuration Registers
D[4]
Don’t Care
Don’t Care
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output
output
Valid
Valid
53 (18.75ns)
80 (12.5ns)
BCR[8] = 0
Data valid in current cycle
BCR[8] = 1
Data valid in next cycle
80 MHz
Undefined
output
output
Valid
Valid