IDT72V283L7-5PF9 IDT, Integrated Device Technology Inc, IDT72V283L7-5PF9 Datasheet - Page 16
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IDT72V283L7-5PF9
Manufacturer Part Number
IDT72V283L7-5PF9
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT72V283L7-5PF9.pdf
(45 pages)
Specifications of IDT72V283L7-5PF9
Configuration
Dual
Density
576Kb
Access Time (max)
5ns
Word Size
9/18Bit
Organization
32Kx18/64Kx9
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
TQFP
Clock Freq (max)
133.3MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.15V
Operating Supply Voltage (max)
3.45V
Supply Current
30@9BIT/35@18BITmA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
80
Lead Free Status / Rohs Status
Not Compliant
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
LD
0
0
0
X
1
1
1
WEN
1
1
0
X
1
0
1
REN
0
1
1
1
X
0
1
SEN
1
1
0
1
X
X
X
WCLK
X
X
X
X
Figure 3. Programmable Flag Offset Programming Sequence (Continued)
RCLK
X
X
X
X
X
Serial shift into registers:
20 bits for the IDT72V223
22 bits for the IDT72V233
24 bits for the IDT72V243
26 bits for the IDT72V253
28 bits for the IDT72V263
30 bits for the IDT72V273
32 bits for the IDT72V283
34 bits for the IDT72V293
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
x9 to x9 Mode
16
TM
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
IDT72V223, IDT72V233
IDT72V243, IDT72V253
IDT72V263, IDT72V273
IDT72V283, IDT72V293
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
NARROW BUS FIFO
Read Memory
No Operation
Write Memory
No Operation
Serial shift into registers:
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
18 bits for the IDT72V223
20 bits for the IDT72V233
22 bits for the IDT72V243
24 bits for the IDT72V253
26 bits for the IDT72V263
28 bits for the IDT72V273
30 bits for the IDT72V283
32 bits for the IDT72V293
COMMERCIAL AND INDUSTRIAL
All Other Modes
TEMPERATURE RANGES
FEBRUARY 11, 2009
4666 drw06a