IDT72V283L7-5PF9 IDT, Integrated Device Technology Inc, IDT72V283L7-5PF9 Datasheet - Page 32
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IDT72V283L7-5PF9
Manufacturer Part Number
IDT72V283L7-5PF9
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT72V283L7-5PF9.pdf
(45 pages)
Specifications of IDT72V283L7-5PF9
Configuration
Dual
Density
576Kb
Access Time (max)
5ns
Word Size
9/18Bit
Organization
32Kx18/64Kx9
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
TQFP
Clock Freq (max)
133.3MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.15V
Operating Supply Voltage (max)
3.45V
Supply Current
30@9BIT/35@18BITmA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
80
Lead Free Status / Rohs Status
Not Compliant
NOTES:
1. x9 to x9 mode: X = 9 for the IDT72V223, X = 10 for the IDT72V233, X = 11 for the IDT72V243, X = 12 for the IDT72V253, X = 13 for the IDT72V263, X = 14 for the IDT72V273,
2. All other modes: X = 8 for the IDT72V223, X = 9 for the IDT72V233, X = 10 for the IDT72V243, X = 11 for the IDT72V253, X = 12 for the IDT72V263, X = 13 for the IDT72V273,
NOTES:
1. If the part is empty at the point of Retransmit, the output ready flag (OR), will be updated based on RCLK (Retransmit clock cycle), valid data will also appear on the output.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure.
3. OE = LOW
4. W
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set LOW during MRS.
WCLK
Q
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
WCLK
RCLK
0
SEN
X = 15 for the IDT72V283 and X = 16 for the IDT72V293.
X = 14 for the IDT72V283 and X = 15 for the IDT72V293.
WEN
REN
- Q
PAE
LD
PAF
1
SI
OR
, W
HF
RT
If x18 Input or x18 Output bus Width is selected, D = 513 for the IDT72V223, 1,025 for the IDT72V233, 2,049 for the IDT72V243, 4,097 for the IDT72V253, 8,193 for the IDT72V263,
16,385 for the IDT72V273, 32,769 for the IDT72V283 and 65,537 for the IDT72V293.
If both x9 Input and x9 Output bus Widths are selected, D = 1,025 for the IDT72V223, 2,049 for the IDT72V233, 4,097 for the IDT72V243, 8,193 for the IDT72V253, 16,385
for the IDT72V263, 32,769 for the IDT72V273, 65,537 for the IDT72V283 and 131,073 for the IDT72V293.
n
2
, W
t
ENS
3
= first, second and third words written to the FIFO after Master Reset.
W
x
Figure 15. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
BIT 0
t
t
ENS
LDS
t
DS
t
ENS
t
W
RTS
x+1
t
t
ENH
LDH
Figure 14. Zero Latency Retransmit Timing (FWFT Mode)
1
t
A
EMPTY OFFSET
t
t
ENH
HF
t
SKEW2
1
W
1
2
t
PAFS
2
t
A
BIT X
32
(1)
TM
W
NARROW BUS FIFO
2
BIT 0
(3)
3
t
A
t
PAES
FULL OFFSET
W
3
(3)
t
4
A
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
BIT X
W
FEBRUARY 11, 2009
4
t
t
t
ENH
LDH
DH
(3)
(1)
5
t
A
t
ENH
4666 drw17
4666 drw18
W
5