CY7C43643-10AC Cypress Semiconductor Corp, CY7C43643-10AC Datasheet - Page 3

• Manufacturer Part Number: CY7C43643-10AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C43643-10AC

• Density: 32Kb
• Word Size: 36b
• Sync/async: Synchronous
• Expandable: Yes
• Package Type: TQFP
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-06021 Rev. *B
Pin Definitions
A
AE
AF
B
BE/FWFT
BM
CLKA
CLKB
CSA
CSB
EF/OR
ENA
ENB
FF/IR
Notes:
Signal Name
1.
2.
0–35
0–35
When reading from the FIFO under FWFT, ORA/ORB signal should be included in the read logic to ensure proper operation. To read without gating the boundary
flag (e.g., in bursts), use CY standard mode.
When FIFO is operated at the almost empty/full boundary, there may be an uncertainty of up to three clock cycles for flag assertion and deassertion. Refer to
“Designing with CY7C436xx Synchronous FIFO” application notes for more details on flag uncertainties.
Port A Data
Almost Empty
Flag (Port B)
Almost Full Flag
Port B Data
Big
Endian/First-Wor
d Fall-Through
Select
Bus Match
Select (Port B)
Port A Clock
Port B Clock
Port A Chip
Select
Port B Chip
Select
Empty/Output
Ready Flag
(Port B)
Port A Enable
Port B Enable
Port B Full/Input
Ready Flag
Description
I/O
O Programmable Almost Empty flag synchronized to CLKA. It is LOW when the
O Programmable Almost Full flag synchronized to CLKA. It is LOW when the number
O 36-bit unidirectional data port for side B.
O This is a dual-function pin. In the CY Standard Mode, the EF function is selected. EF
O This is a dual-function pin. In the CY Standard Mode, the FF function is selected. FF
I
I
I
I
I
I
I
I
I
36-bit unidirectional data port for side A.
number of words in the FIFO2 is less than or equal to the value in the Almost Empty A
offset register, X.
of empty locations in the FIFO is less than or equal to the value in the Almost Full A
offset register, Y.
This is a dual-purpose pin. During Master Reset, a HIGH on BE will select Big Endian
operation. In this case, depending on the bus size, the most significant byte or word on
Port A is transferred to Port B first. A LOW on BE will select Little Endian operation. In
this case, the least significant byte or word on Port A is transferred to Port B first. After
Master Reset, this pin selects the timing mode. A HIGH on FWFT selects CY Standard
Mode, a LOW selects First-Word Fall-Through Mode. Once the timing mode has been
selected, the level on FWFT must be static throughout device operation.
A HIGH on this pin enables either byte or word bus width on Port B, depending on
the state of SIZE. A LOW selects long-word operation. BM works with SIZE and BE to
select the bus size and endian arrangement for Port B. The level of BM must be static
throughout device operation.
CLKA is a continuous clock that synchronizes all data transfers through Port A
and can be asynchronous or coincident to CLKB. FF/IR and AF are all synchronized to
the LOW-to-HIGH transition of CLKA.
CLKB is a continuous clock that synchronizes all data transfers through Port B
and can be asynchronous or coincident to CLKA. FB/IR, EF/OR, AF, and AE are all
synchronized to the LOW-to-HIGH transition of CLKB.
CSA must be LOW to enable a LOW-to HIGH transition of CLKA to read or write on
Port A. The A
CSB must be LOW to enable a LOW-to HIGH transition of CLKB to read or write on
Port B. The B
indicates whether or not the FIFO memory is empty. In the FWFT mode, the OR function
is selected. OR indicates the presence of valid data on A
reading. EF/OR is synchronized to the LOW-to-HIGH transition of CLKB.
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write
data on Port A.
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write
data on Port B.
indicates whether or not the FIFO memory is full. In the FWFT mode, the IR function is
selected. IR indicates whether or not there is space available for writing to the FIFO
memory. FF/IR is synchronized to the LOW-to-HIGH transition of CLKA.
0–35
0–35
[1]
[1]
outputs are in the high-impedance state when CSA is HIGH.
outputs are in the high-impedance state when CSB is HIGH.
Function
0–35
outputs, available for
CY7C43643
CY7C43663
CY7C43683
[2]
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