CY7C43643-10AC Cypress Semiconductor Corp, CY7C43643-10AC Datasheet - Page 7

• Manufacturer Part Number: CY7C43643-10AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C43643-10AC

• Density: 32Kb
• Word Size: 36b
• Sync/async: Synchronous
• Expandable: Yes
• Package Type: TQFP
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-06021 Rev. *B
lines are in the high-impedance state when either CSB is HIGH
or W/RB is LOW. The B
is LOW and W/RB is HIGH.
Data is read from the FIFO to the B
LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is
HIGH, ENB is HIGH, MBB is LOW, and EF/OR is HIGH (see
Table 4). FIFO reads and writes on Port B are independent of
any concurrent Port A operation.
The Set-up and hold time constraints to the port clocks for the
port Chip Selects and Write/Read Selects are only for enabling
write and read operations and are not related to
high-impedance control of the data outputs. If a port enable is
LOW during a clock cycle, the port’s Chip Select and
Write/Read Select may change states during the Set-up and
hold time window of the cycle.
When operating the FIFO in FWFT Mode with the Output
Ready flag LOW, the next word written is automatically sent to
the FIFO’s output register by the LOW-to-HIGH transition of
the port clock that sets the Output Ready flag HIGH, data
residing in the FIFO’s memory array is clocked to the output
register only when a read is selected using the port’s Chip
Select, Write/Read Select, Enable, and Mailbox Select.
When operating the FIFO in CY Standard Mode, regardless of
whether the Empty Flag is LOW or HIGH, data residing in the
FIFO’s memory array is clocked to the output register only
when a read is selected using the port’s Chip Select,
Write/Read Select, Enable, and Mailbox Select.
Synchronized FIFO Flags
Each FIFO is synchronized to its port clock through at least two
flip-flop stages. This is done to improve flag-signal reliability by
reducing the probability of the metastable events when CLKA
and CLKB operate asynchronously to one another. EF/OR and
AE are synchronized to CLKA. FF/IR and AF are synchronized
to CLKB. Table 5 shows the relationship of each port flag to
the FIFO.
Empty/Output Ready Flags (EF/OR)
These are dual-purpose flags. In the FWFT Mode, the Output
Ready (OR) function is selected. When the Output Ready flag
is HIGH, new data is present in the FIFO output register. When
the Output Ready flag is LOW, the previous data word is
present in the FIFO output register and attempted FIFO reads
are ignored.
In the CY Standard Mode, the Empty Flag (EF) function is
selected. When the Empty Flag is HIGH, data is available in
the FIFO’s RAM memory for reading to the output register.
When the Empty Flag is LOW, the previous data word is
present in the FIFO output register and attempted FIFO reads
are ignored.
The Empty/Output Ready flag of a FIFO is synchronized to the
port clock that reads data from its array. For both the FWFT
and CY Standard modes, the FIFO read pointer is incremented
each time a new word is clocked to its output register. The
state machine that controls an Output Ready flag monitors a
write pointer and read pointer comparator that indicates when
the FIFO SRAM status is empty, or empty+1.
In FWFT Mode, from the time a word is written to a FIFO, it
can be shifted to the FIFO output register in a minimum of
three cycles of the Output Ready flag synchronizing clock.
Therefore, an Output Ready flag is LOW if a word in memory
[1]
0–35
lines are active outputs when CSB
0–35
outputs by a
is the next data to be sent to the FIFO output register and three
cycles have not elapsed since the time the word was written.
The Output Ready flag of the FIFO remains LOW until the third
LOW-to-HIGH transition of the synchronizing clock occurs,
simultaneously forcing the Output Ready flag HIGH and
shifting the word to the FIFO output register.
In the CY Standard Mode, from the time a word is written to a
FIFO, the Empty Flag will indicate the presence of data
available for reading in a minimum of two cycles of the Empty
Flag synchronizing clock. Therefore, an Empty Flag is LOW if
a word in memory is the next data to be sent to the FIFO output
register and two cycles have not elapsed since the time the
word was written. The Empty Flag of the FIFO remains LOW
until the second LOW-to-HIGH transition of the synchronizing
clock occurs, forcing the Empty Flag HIGH; only then can data
be read.
A LOW-to-HIGH transition on an Empty/Output Ready flag
synchronizing clock begins the first synchronization cycle of a
write if the clock transition occurs at time t
after the write. Otherwise, the subsequent clock cycle can be
the first synchronization cycle.
Full/Input Ready Flags (FF/IR)
This is a dual-purpose flag. In FWFT Mode, the Input Ready
(IR) function is selected. In CY Standard Mode, the Full Flag
(FF) function is selected. For both timing modes, when the
Full/Input Ready flag is HIGH, a memory location is free in the
SRAM to receive new data. No memory locations are free
when the Full/Input Ready flag is LOW and attempted writes
to the FIFO are ignored.
The Full/Input Ready flag of a FIFO is synchronized to the port
clock that writes data to its array. For both FWFT and CY
Standard modes, each time a word is written to a FIFO, its
write pointer is incremented. The state machine that controls
a Full/Input Ready flag monitors a write pointer and read
pointer comparator that indicates when the FIFO SRAM status
is full, or full–1. From the time a word is read from a FIFO, its
previous memory location is ready to be written to in a
minimum of two cycles of the Full/Input Ready flag synchro-
nizing clock. Therefore, an Full/Input Ready flag is LOW if less
than two cycles of the Full/Input Ready flag synchronizing
clock have elapsed since the next memory write location has
been read. The second LOW-to-HIGH transition on the
Full/Input Ready flag synchronizing clock after the read sets
the Full/Input Ready flag HIGH.
A LOW-to-HIGH transition on a Full/Input Ready flag synchro-
nizing clock begins the first synchronization cycle of a read if
the clock transition occurs at time t
read. Otherwise, the subsequent clock cycle can be the first
synchronization cycle.
Almost Empty Flags (AE)
The Almost Empty flag of the FIFO is synchronized to port B
clock. The state machine that controls an Almost Empty flag
monitors a write pointer and read pointer comparator that
indicates when the FIFO SRAM status is almost empty, or
almost empty+1. The Almost Empty state is defined by the
contents of register X for AE. These registers are loaded with
preset values during a FIFO reset, programmed from Port A,
or programmed serially (see Almost Empty flag and Almost
Full flag offset programming above). An Almost Empty flag is
LOW when its FIFO contains X or less words and is HIGH
when its FIFO contains (X+1) or more words
SKEW1
CY7C43643
CY7C43663
CY7C43683
or greater after the
SKEW1
[2]
.
Page 7 of 29
or greater
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