MAX5548ETE+T Maxim Integrated Products, MAX5548ETE+T Datasheet - Page 10

• Manufacturer Part Number: MAX5548ETE+T
• Description: IC DAC 8BIT DUAL 30MA 16-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX5548ETE+T

• Settling Time: 30µs
• Number Of Bits: 8
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -

The MAX5548 recognizes a STOP condition at any point
during transmission except if a STOP condition occurs in
the same high pulse as a START condition
This condition is not allowed in the I
A repeated START (S
master is writing to several I
want to relinquish control of the bus. The MAX5548’s
serial interface supports continuous write operations
with an S
Successful data transfers are acknowledged with an
acknowledge bit (ACK). Both the master and the
MAX5548 (slave) generate acknowledge bits. To gen-
erate an acknowledge, the receiving device must pull
SDA low before the rising edge of the acknowledge-
related clock pulse (ninth pulse) and keep it low during
the high period of the clock pulse (Figure 5).
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer happens if a receiving device is busy or if a
system fault has occurred. In the event of an unsuc-
cessful data transfer, the master should reattempt com-
munication at a later time.
A master initiates communication with a slave device
by issuing a START condition followed by a slave
address (see Table 3). The slave address consists of 7
Dual, 8-Bit, Programmable, 30mA
High-Output-Current DAC
Figure 2. I
10
SDA
SCL
t
______________________________________________________________________________________
SU:STA
t
FDA
2
r
C Serial-Interface Timing Diagram
condition separating them.
S
t
r
HD:STA
) condition is used when the bus
t
RCL
Repeated START Conditions
t
RDA
2
C devices and does not
Acknowledge Bit (ACK)
Early STOP Conditions
t
HIGH
t
HD:DAT
2
C format.
t
FCL
Slave Address
t
LOW
t
SU:DAT
(Figure 4).
t
Figure 3. START and STOP Conditions
Figure 4. Early STOP Conditions
FCL
t
LOW
SDA
SCL
SDA
SDA
SCL
SCL
S
t
HIGH
LEGAL STOP CONDITION
ILLEGAL EARLY STOP CONDITION
START
STOP
Sr
t
RCL
ILLEGAL
START
STOP
t
SU:STO
Sr
P
P