MAX5548ETE+T Maxim Integrated Products, MAX5548ETE+T Datasheet - Page 9

• Manufacturer Part Number: MAX5548ETE+T
• Description: IC DAC 8BIT DUAL 30MA 16-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX5548ETE+T

• Settling Time: 30µs
• Number Of Bits: 8
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -

and SCL (I
mode) facilitate communication between the MAX5548
and the master. The serial interface remains active
in shutdown.
The MAX5548 is compatible with existing I
(Figure 2). SCL and SDA are high-impedance inputs;
SDA has an open-drain output that pulls the data line
low during the ninth clock pulse. SDA and SCL require
pullup resistors (2.4kΩ or greater) to V
resistors (24Ω) in series with SDA and SCL protect the
device inputs from high-voltage spikes on the bus lines.
Series resistors also minimize crosstalk and undershoot
of the bus signals. The communication protocol sup-
ports standard I
address is compatible with 7-bit I
col only. Ten-bit address formats are not supported.
Only write commands are accepted by the MAX5548.
Note: I
Table 1. Full-Scale Output Current and R
Reference Voltage
*See the command summary in Table 4.
Figure 1. Reference Architecture and Output Current Adjustment
I
FSADJ
1mA–2mA
1.00
1.25
1.50
1.75
2.00
2
R
C readback is not supported.
FSADJ
2
FSADJ_
I
C mode) and DIN, SCLK, and CS (SPI
2
C Compatibility (SPI/ I2C = GND)
REFERENCE
2
1.5mA–3mA
C 8-bit communications. The device’s
+1.25V
_______________________________________________________________________________________
1.500
1.875
2.250
2.625
3.000
FULL-SCALE OUTPUT CURRENT (mA)*
CURRENT-SOURCE
2.5mA–5mA
ARRAY DAC
V
2
2.500
3.125
3.750
4.375
5.000
DD
C addressing proto-
Dual, 8-Bit, Programmable, 30mA
GND
DD
2
C systems
. Optional
4.5mA–9mA
OUT_
4.500
5.625
6.750
7.875
9.000
FSADJ_
High-Output-Current DAC
8mA–16mA
One data bit transfers during each SCL rising edge.
The MAX5548 requires nine clock cycles to transfer
data into or out of the DAC register. The data on SDA
must remain stable during the high period of the SCL
clock pulse. Changes in SDA while SCL is high are
read as control signals (see the START and STOP
Conditions section). Both SDA and SCL idle high.
The master initiates a transmission with a START condi-
tion (S), (a high-to-low transition on SDA with SCL high).
The master terminates a transmission with a STOP con-
dition (P), (a low-to-high transition on SDA while SCL is
high) (Figure 3). A START condition from the master sig-
nals the beginning of a transmission to the MAX5548.
The master terminates transmission by issuing a STOP
condition. The STOP condition frees the bus.
If a repeated START condition (S
of a STOP condition, the bus remains active.
Table 2. DAC Output Code Table
*Negative output current values = 0.
10.00
12.00
14.00
16.00
8.00
Selection Based on a +1.25V (typ)
DAC CODE
0000 0001*
1111 1111
1000 0000
0000 0000
15mA–30mA
15.00
18.75
22.50
26.25
30.00
START and STOP Conditions
Calculated
r
40
35
30
25
20
255
128
) is generated instead
R
×
×
I
FSADJ
OUT
256
I
256
I
FS
FS
0
256
I
FS
_
−
−
−
Bit Transfer
(kΩ)
|
|
1% EIA Std.
I
I
|
OS
OS
I
OS
40.2
34.8
30.1
24.9
20.0
|
|
|
9