72T36125L4-4BB Integrated Device Technology (Idt), 72T36125L4-4BB Datasheet - Page 31

• Manufacturer Part Number: 72T36125L4-4BB
• Description: FIFO Mem Async/Sync Dual Depth/Width Uni-Dir 256K x 36 240-Pin BGA
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72T36125L4-4BB

• Package: 240BGA
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 9 Mb
• Organization: 256Kx36
• Data Bus Width: 36 Bit
• Timing Type: Asynchronous|Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 2.5 V
• Operating Temperature: 0 to 70 °C

JTAG TIMING SPECIFICATION
SYSTEM INTERFACE PARAMETERS
NOTE:
1. 50pf loading on external output signals.
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
Data Output Hold
TRST
Data Output
Parameter
TDI/
TMS
TDO
TCK
Data Input
Symbol Test Conditions
t
t
DOH
DO
t
t
DS
DH
t
3
t
(1)
(1)
5
t
t
rise=3ns
fall=3ns
t
1
t
6
t
DS
t
4
t
TCK
Min.
10
10
0
t
-
DH
IDT72T36105
IDT72T36115
IDT72T36125
IDT72T3645
IDT72T3655
IDT72T3665
IDT72T3675
IDT72T3685
IDT72T3695
Figure 6. Standard JTAG Timing
Notes to diagram:
t1 = t
t2 = t
t3 = t
t4 = t
t5 = tRST
t6 = tRSR (reset recovery)
t
Max. Units
2
20
-
-
-
TCKRISE
TCKLOW
TCKHIGH
TCKFALL
ns
ns
ns
(reset pulse width)
31
(v
NOTE:
1. Guaranteed by design.
JTAG
AC ELECTRICAL CHARACTERISTICS
JTAG Clock Input Period t
JTAG Clock HIGH
JTAG Clock Low
JTAG Clock Rise Time
JTAG Clock Fall Time
JTAG Reset
JTAG Reset Recovery
cc = 2.5V
Parameter
±
5%; Tcase = 0°C to +85°C)
Symbol
t
t
t
t
t
t
TCK
TCKHIGH
TCKLOW
TCKRISE
TCKFALL
RST
RSR
COMMERCIAL AND INDUSTRIAL
Conditions
t
DO
Test
TEMPERATURE RANGES
-
-
-
-
-
-
-
FEBRUARY 4, 2009
Min. Max. Units
100
40
40
50
50
-
-
TDO
5
5
-
-
-
-
-
(1)
(1)
5907 drw11
ns
ns
ns
ns
ns
ns
ns