72T36125L4-4BB Integrated Device Technology (Idt), 72T36125L4-4BB Datasheet - Page 39

• Manufacturer Part Number: 72T36125L4-4BB
• Description: FIFO Mem Async/Sync Dual Depth/Width Uni-Dir 256K x 36 240-Pin BGA
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72T36125L4-4BB

• Package: 240BGA
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 9 Mb
• Organization: 256Kx36
• Data Bus Width: 36 Bit
• Timing Type: Asynchronous|Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 2.5 V
• Operating Temperature: 0 to 70 °C

NOTES:
1. t
2. LD = HIGH.
3. First data word latency = t
4. OE is LOW.
Q0 - Qn
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
WCLK
RCLK
rising edge of WCLK and the rising edge of RCLK is less than t
WEN
SKEW1
RCS
REN
Dn
EF
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus t
t
t
ENS
ENS
t
RCSLZ
t
ENH
SKEW1
t
A
+ 1*T
LAST DATA-1
RCLK
Figure 13. Read Cycle and Read Chip Select (IDT Standard Mode)
+ t
REF.
t
RCSHZ
SKEW1
t
ENS
, then EF deassertion may be delayed one extra RCLK cycle.
t
RCSLZ
t
REF
39
t
A
t
t
ENS
DS
LAST DATA
D
t
ENS
x
t
SKEW1
t
ENH
t
DH
(1)
1
t
RCSHZ
COMMERCIAL AND INDUSTRIAL
2
TEMPERATURE RANGES
t
REF
REF
FEBRUARY 4, 2009
). If the time between the
5907 drw 18