72T36125L4-4BB Integrated Device Technology (Idt), 72T36125L4-4BB Datasheet - Page 6

• Manufacturer Part Number: 72T36125L4-4BB
• Description: FIFO Mem Async/Sync Dual Depth/Width Uni-Dir 256K x 36 240-Pin BGA
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72T36125L4-4BB

• Package: 240BGA
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 9 Mb
• Organization: 256Kx36
• Data Bus Width: 36 Bit
• Timing Type: Asynchronous|Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 2.5 V
• Operating Temperature: 0 to 70 °C

TABLE 1 — BUS-MATCHING CONFIGURATION MODES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
NOTE:
1. Pin status during Master Reset.
BM
H
H
H
H
L
PROGRAMMABLE ALMOST-FULL (PAF)
FULL FLAG/INPUT READY (FF/IR)
FIRST WORD FALL THROUGH/
(x36, x18, x9) DATA IN (D
WRITE CHIP SELECT (WCS)
WRITE CLOCK (WCLK/WR)
SERIAL INPUT (FWFT/SI)
SERIAL CLOCK (SCLK)
WRITE ENABLE (WEN)
SERIAL ENABLE(SEN)
I W
H
H
L
L
L
Figure 1. Single Device Configuration Signal Flow Diagram
PARTIAL RESET (PRS)
INPUT WIDTH (IW)
LOAD (LD)
0
- D
n
)
OW
H
H
L
L
L
MATCHING
72T36105
72T36115
72T36125
72T3645
72T3655
72T3665
72T3675
72T3685
72T3695
(BM)
BUS-
IDT
6
MASTER RESET (MRS)
OUTPUT WIDTH (OW)
REN ECHO, EREN
READ CLOCK (RCLK/RD)
READ ENABLE (REN)
RCLK ECHO, ERCLK
RETRANSMIT (RT)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
HALF-FULL FLAG (HF)
BIG-ENDIAN/LITTLE-ENDIAN (BE)
INTERSPERSED/
NON-INTERSPERSED PARITY (IP)
(x36, x18, x9) DATA OUT (Q
MARK
OUTPUT ENABLE (OE)
READ CHIP SELECT (RCS)
Write Port Width
x36
x36
x36
x18
x9
COMMERCIAL AND INDUSTRIAL
0
- Q
TEMPERATURE RANGES
n
Read Port Width
)
5907 drw03
FEBRUARY 4, 2009
x36
x18
x36
x36
x9