ST72F324BK6TAS STMicroelectronics, ST72F324BK6TAS Datasheet - Page 31

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ST72F324BK6TAS

Manufacturer Part Number
ST72F324BK6TAS
Description
8-BIT MCU
Manufacturer
STMicroelectronics
Datasheet
ST72324B-Auto
6
6.1
6.2
Caution:
Supply, reset and clock management
Introduction
The device includes a range of utility features for securing the application in critical
situations (for example in case of a power brown-out), and reducing the number of external
components. An overview is shown in
For more details, refer to dedicated parametric section.
Main features
PLL (phase locked loop)
If the clock frequency input to the PLL is in the range 2 to 4 MHz, the PLL can be used to
multiply the frequency by two to obtain an f
byte. If the PLL is disabled, then f
The PLL is not recommended for applications where timing accuracy is required.
Furthermore, it must not be used with the internal RC oscillator.
Figure 9.
Optional Phase Locked Loop (PLL) for multiplying the frequency by 2 (not to be used
with internal RC oscillator in order to respect the max. operating frequency)
Multi-Oscillator clock management (MO)
Reset Sequence Manager (RSM)
System Integrity management (SI)
5 crystal/ceramic resonator oscillators
1 Internal RC oscillator
Main supply low voltage detection (LVD)
Auxiliary voltage detector (AVD) with interrupt capability for monitoring the main
supply
PLL block diagram
f
OSC
Doc ID13466 Rev 4
OSC2
PLL x 2
Figure
= f
/ 2
OSC
OSC2
10.
/2.
of 4 to 8 MHz. The PLL is enabled by option
PLL option bit
Supply, reset and clock management
0
1
f
OSC2
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