USB3280-AEZG-TR Standard Microsystems (SMSC), USB3280-AEZG-TR Datasheet - Page 33

• Manufacturer Part Number: USB3280-AEZG-TR
• Manufacturer: Standard Microsystems (SMSC)

Hi-Speed USB Device PHY with UTMI Interface
Datasheet
SMSC USB3280
PARAMETER
TIMING
T0
T1
T2
T3
T4
T5
Notes:
T0 may occur to 4ms after HS Reset T0.
The SIE must assert the Chirp K for 66000 CLKOUT cycles to ensure a 1ms minimum duration.
HS Handshake begins. DP pull-up enabled, HS
terminations disabled.
Device enables HS Transceiver and asserts Chirp
K on the bus.
Device removes Chirp K from the bus. 1ms
minimum width.
Earliest time when downstream facing port may
assert Chirp KJ sequence on the bus.
Chirp not detected by the device. Device reverts to
FS default state and waits for end of reset.
Earliest time at which host port may end reset
Figure 8.3 HS Detection Handshake Timing Behavior (FS Mode)
Table 8.6 HS Detection Handshake Timing Values (FS Mode)
DESCRIPTION
DATASHEET
33
HS Reset T0 + 10ms
0 (reference)
T0 < T1 < HS Reset T0 + 6.0ms
T1 + 1.0 ms < T2 <
HS Reset T0 + 7.0ms
T2 < T3 < T2+100µs
T2 + 1.0ms < T4 <
T2 + 2.5ms
VALUE
Revision 1.5 (11-15-07)