EPM7160STI100-10 Altera, EPM7160STI100-10 Datasheet - Page 22
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EPM7160STI100-10
Manufacturer Part Number
EPM7160STI100-10
Description
IC MAX 7000 CPLD 160 100-TQFP
Manufacturer
Altera
Series
MAX® 7000r
Datasheet
1.EPM7064STC44-10.pdf
(66 pages)
Specifications of EPM7160STI100-10
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
4.5 V ~ 5.5 V
Number Of Logic Elements/blocks
10
Number Of Macrocells
160
Number Of Gates
3200
Number Of I /o
84
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Voltage
5V
Memory Type
EEPROM
Number Of Logic Elements/cells
10
Family Name
MAX 7000S
# Macrocells
160
Number Of Usable Gates
3200
Frequency (max)
125MHz
Propagation Delay Time
10ns
Number Of Logic Blocks/elements
10
# I/os (max)
84
Operating Supply Voltage (typ)
5V
In System Programmable
Yes
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Package Type
TQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-2052
EPM7160STI100-10
EPM7160STI100-10
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Part Number
Manufacturer
Quantity
Price
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MAX 7000 Programmable Logic Device Family Data Sheet
IEEE Std.
1149.1 (JTAG)
Boundary-Scan
Support
22
SAMPLE/PRELOAD
EXTEST
BYPASS
IDCODE
ISP Instructions
Table 9. MAX 7000 JTAG Instructions
JTAG Instruction
EPM7128S
EPM7160S
EPM7192S
EPM7256S
EPM7128S
EPM7160S
EPM7192S
EPM7256S
EPM7032S
EPM7064S
EPM7128S
EPM7160S
EPM7192S
EPM7256S
EPM7032S
EPM7064S
EPM7128S
EPM7160S
EPM7192S
EPM7256S
EPM7032S
EPM7064S
EPM7128S
EPM7160S
EPM7192S
EPM7256S
Devices
MAX 7000 devices support JTAG BST circuitry as specified by IEEE Std.
1149.1-1990.
MAX 7000 family. The pin-out tables (see the Altera web site
(http://www.altera.com) or the Altera Digital Library for pin-out
information) show the location of the JTAG control pins for each device.
If the JTAG interface is not required, the JTAG pins are available as user
I/O pins.
Allows a snapshot of signals at the device pins to be captured and
examined during normal device operation, and permits an initial data
pattern output at the device pins.
Allows the external circuitry and board-level interconnections to be
tested by forcing a test pattern at the output pins and capturing test
results at the input pins.
Places the 1-bit bypass register between the TDI and TDO pins, which
allows the BST data to pass synchronously through a selected device
to adjacent devices during normal device operation.
Selects the IDCODE register and places it between TDI and TDO,
allowing the IDCODE to be serially shifted out of TDO.
These instructions are used when programming MAX 7000S devices
via the JTAG ports with the MasterBlaster, ByteBlasterMV, BitBlaster
download cable, or using a Jam File (.jam), Jam Byte-Code file (.jbc),
or Serial Vector Format file (.svf) via an embedded processor or test
equipment.
Table 9
describes the JTAG instructions supported by the
Description
Altera Corporation