EPM7160STI100-10 Altera, EPM7160STI100-10 Datasheet - Page 34
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EPM7160STI100-10
Manufacturer Part Number
EPM7160STI100-10
Description
IC MAX 7000 CPLD 160 100-TQFP
Manufacturer
Altera
Series
MAX® 7000r
Datasheet
1.EPM7064STC44-10.pdf
(66 pages)
Specifications of EPM7160STI100-10
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
4.5 V ~ 5.5 V
Number Of Logic Elements/blocks
10
Number Of Macrocells
160
Number Of Gates
3200
Number Of I /o
84
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Voltage
5V
Memory Type
EEPROM
Number Of Logic Elements/cells
10
Family Name
MAX 7000S
# Macrocells
160
Number Of Usable Gates
3200
Frequency (max)
125MHz
Propagation Delay Time
10ns
Number Of Logic Blocks/elements
10
# I/os (max)
84
Operating Supply Voltage (typ)
5V
In System Programmable
Yes
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Package Type
TQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-2052
EPM7160STI100-10
EPM7160STI100-10
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM7160STI100-10
Manufacturer:
ALTERA
Quantity:
5 530
Part Number:
EPM7160STI100-10
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EPM7160STI100-10N
Manufacturer:
ALTERA
Quantity:
1 000
Company:
Part Number:
EPM7160STI100-10N
Manufacturer:
ALTERA
Quantity:
5 530
Company:
Part Number:
EPM7160STI100-10N
Manufacturer:
ALTERA31
Quantity:
217
Part Number:
EPM7160STI100-10N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
MAX 7000 Programmable Logic Device Family Data Sheet
34
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Symbol
IN
IO
FIN
SEXP
PEXP
LAD
LAC
IOE
OD1
OD2
OD3
ZX1
ZX2
ZX3
XZ
SU
H
FSU
FH
RD
COMB
IC
EN
GLOB
PRE
CLR
PIA
LPA
Table 22. MAX 7000 & MAX 7000E Internal Timing Parameters
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad delay
Slow slew rate = off
V
Output buffer and pad delay
Slow slew rate = off
V
Output buffer and pad delay
Slow slew rate = on
V
Output buffer enable delay
Slow slew rate = off
V
Output buffer enable delay
Slow slew rate = off
V
Output buffer enable delay
Slow slew rate = on
V
Output buffer disable delay
Register setup time
Register hold time
Register setup time of fast input
Register hold time of fast input
Register delay
Combinatorial delay
Array clock delay
Register enable time
Global control delay
Register preset time
Register clear time
PIA delay
Low-power adder
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
= 5.0 V
= 3.3 V
= 5.0 V or 3.3 V
= 5.0 V
= 3.3 V
= 5.0 V or 3.3 V
Parameter
(2)
(2)
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
(2)
(2)
(8)
C1 = 5 pF
Conditions
(7)
(2)
(7)
(2)
MAX 7000E (-10P) MAX 7000 (-10)
Min
2.0
3.0
3.0
0.5
Note (1)
11.0
Max
Speed Grade
0.5
0.5
1.0
5.0
0.8
5.0
5.0
2.0
1.5
2.0
5.5
5.0
5.5
9.0
5.0
2.0
2.0
5.0
5.0
1.0
3.0
3.0
1.0
MAX 7000E (-10)
Min
3.0
3.0
3.0
0.5
Altera Corporation
11.0
Max
1.0
1.0
5.0
1.0
1.0
1.0
5.0
0.8
5.0
5.0
2.0
2.0
2.5
6.0
5.0
5.5
9.0
5.0
5.0
1.0
3.0
3.0
1.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns