EPM7128AETC100-10N Altera, EPM7128AETC100-10N Datasheet - Page 12

IC MAX 7000 CPLD 128 100-TQFP

EPM7128AETC100-10N

Manufacturer Part Number
EPM7128AETC100-10N
Description
IC MAX 7000 CPLD 128 100-TQFP
Manufacturer
Altera
Series
MAX® 7000Ar
Datasheet

Specifications of EPM7128AETC100-10N

Programmable Type
In System Programmable
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
8
Number Of Macrocells
128
Number Of Gates
2500
Number Of I /o
84
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Voltage
3.3V
Memory Type
EEPROM
Number Of Logic Elements/cells
8
Cpld Type
EEPROM
No. Of Macrocells
128
No. Of I/o's
84
Propagation Delay
10ns
Global Clock Setup Time
6.6ns
Frequency
98MHz
Supply Voltage Range
3V To 3.6V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
544-2027
EPM7128AETC100-10N

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MAX 7000A Programmable Logic Device Data Sheet
Figure 4. MAX 7000A Parallel Expanders
12
Unused product terms in a macrocell can be allocated to a neighboring macrocell.
36 Signals
from PIA
Expanders
16 Shared
Programmable Interconnect Array
Logic is routed between LABs on the PIA. This global bus is a
programmable path that connects any signal source to any destination on
the device. All MAX 7000A dedicated inputs, I/O pins, and macrocell
outputs feed the PIA, which makes the signals available throughout the
entire device. Only the signals required by each LAB are actually routed
from the PIA into the LAB.
into the LAB. An EEPROM cell controls one input to a 2-input AND gate,
which selects a PIA signal to drive into the LAB.
Product-
Product-
Select
Select
Matrix
Matrix
Term
Term
Macrocell
Previous
From
Figure 5
shows how the PIA signals are routed
Macrocell
To Next
Preset
Preset
Clock
Clear
Clock
Clear
Altera Corporation
Macrocell
Product-
Term Logic
Macrocell
Product-
Term Logic

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