EPM7128AETC100-10N Altera, EPM7128AETC100-10N Datasheet - Page 2
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EPM7128AETC100-10N
Manufacturer Part Number
EPM7128AETC100-10N
Description
IC MAX 7000 CPLD 128 100-TQFP
Manufacturer
Altera
Series
MAX® 7000Ar
Datasheet
1.EPM7032AELC44-10N.pdf
(64 pages)
Specifications of EPM7128AETC100-10N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
8
Number Of Macrocells
128
Number Of Gates
2500
Number Of I /o
84
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Voltage
3.3V
Memory Type
EEPROM
Number Of Logic Elements/cells
8
Cpld Type
EEPROM
No. Of Macrocells
128
No. Of I/o's
84
Propagation Delay
10ns
Global Clock Setup Time
6.6ns
Frequency
98MHz
Supply Voltage Range
3V To 3.6V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
544-2027
EPM7128AETC100-10N
EPM7128AETC100-10N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM7128AETC100-10N
Manufacturer:
ALTERA
Quantity:
1 920
Company:
Part Number:
EPM7128AETC100-10N
Manufacturer:
ALTERA74
Quantity:
350
Part Number:
EPM7128AETC100-10N
Manufacturer:
ALTERA
Quantity:
20 000
MAX 7000A Programmable Logic Device Data Sheet
...and More
Features
2
Usable gates
Macrocells
Logic array blocks
Maximum user I/O
pins
t
t
t
t
f
PD
SU
FSU
CO1
CNT
Table 1. MAX 7000A Device Features
(ns)
(ns)
(ns)
(ns)
(MHz)
Feature
EPM7032AE
227.3
600
4.5
2.9
2.5
3.0
32
36
2
4.5-ns pin-to-pin logic delays with counter frequencies of up to
227.3 MHz
MultiVolt
I/O pins are compatible with 5.0-V, 3.3-V, and 2.5-V logic levels
Pin counts ranging from 44 to 256 in a variety of thin quad flat pack
(TQFP), plastic quad flat pack (PQFP), ball-grid array (BGA), space-
saving FineLine BGA
packages
Supports hot-socketing in MAX 7000AE devices
Programmable interconnect array (PIA) continuous routing structure
for fast, predictable performance
PCI-compatible
Bus-friendly architecture, including programmable slew-rate control
Open-drain output option
Programmable macrocell registers with individual clear, preset,
clock, and clock enable controls
Programmable power-up states for macrocell registers in
MAX 7000AE devices
Programmable power-saving mode for 50% or greater power
reduction in each macrocell
Configurable expander product-term distribution, allowing up to
32 product terms per macrocell
Programmable security bit for protection of proprietary designs
6 to 10 pin- or logic-driven output enable signals
Two global clock signals with optional inversion
Enhanced interconnect resources for improved routability
Fast input setup times provided by a dedicated path from I/O pin to
macrocell registers
Programmable output slew-rate control
Programmable ground pins
EPM7064AE
1,250
222.2
4.5
2.8
2.5
3.1
64
68
TM
4
I/O interface enables device core to run at 3.3 V, while
TM
EPM7128AE
, and plastic J-lead chip carrier (PLCC)
2,500
192.3
128
100
5.0
3.3
2.5
3.4
8
EPM7256AE
5,000
172.4
256
164
5.5
3.9
2.5
3.5
16
Altera Corporation
EPM7512AE
10,000
116.3
512
212
7.5
5.6
3.0
4.7
32