EPM1270T144C4 Altera, EPM1270T144C4 Datasheet - Page 25
![IC MAX II CPLD 1270 LE 144-TQFP](/photos/6/70/67061/544-144-tqfp_sml.jpg)
EPM1270T144C4
Manufacturer Part Number
EPM1270T144C4
Description
IC MAX II CPLD 1270 LE 144-TQFP
Manufacturer
Altera
Series
MAX® IIr
Specifications of EPM1270T144C4
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
6.2ns
Voltage Supply - Internal
2.5V, 3.3V
Number Of Logic Elements/blocks
1270
Number Of Macrocells
980
Number Of I /o
116
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
144-TQFP, 144-VQFP
Voltage
2.5V, 3.3V
Memory Type
FLASH
Number Of Logic Elements/cells
1270
For Use With
544-2380 - KIT DEV MAXII W/EPM 1270N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Other names
544-1142
544-1325
544-1325
EPM1270T144C4ES
544-1325
544-1325
EPM1270T144C4ES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EPM1270T144C4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Chapter 2: MAX II Architecture
Global Signals
© October 2008 Altera Corporation
Figure 2–13. Global Clock Generation
Note to
(1) Any I/O pin can use a MultiTrack interconnect to route as a logic array-generated global clock signal.
The global clock network drives to individual LAB column signals, LAB column
clocks [3..0], that span an entire LAB column from the top to the bottom of the device.
Unused global clocks or control signals in a LAB column are turned off at the LAB
column clock buffers shown in
multiplexed down to two LAB clock signals and one LAB clear signal. Other control
signal types route from the global clock network into the LAB local interconnect. See
“LAB Control Signals” on page 2–5
Figure 2–13
:
Logic Array(1)
GCLK0
GCLK1
GCLK2
GCLK3
Figure
for more information.
4
2–14. The LAB column clocks [3..0] are
4
Global Clock
Network
MAX II Device Handbook
2–17