EPM1270T144C4 Altera, EPM1270T144C4 Datasheet - Page 73

IC MAX II CPLD 1270 LE 144-TQFP

EPM1270T144C4

Manufacturer Part Number
EPM1270T144C4
Description
IC MAX II CPLD 1270 LE 144-TQFP
Manufacturer
Altera
Series
MAX® IIr
Datasheets

Specifications of EPM1270T144C4

Programmable Type
In System Programmable
Delay Time Tpd(1) Max
6.2ns
Voltage Supply - Internal
2.5V, 3.3V
Number Of Logic Elements/blocks
1270
Number Of Macrocells
980
Number Of I /o
116
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
144-TQFP, 144-VQFP
Voltage
2.5V, 3.3V
Memory Type
FLASH
Number Of Logic Elements/cells
1270
For Use With
544-2380 - KIT DEV MAXII W/EPM 1270N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Other names
544-1142
544-1325
544-1325
EPM1270T144C4ES

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EPM1270T144C4
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EPM1270T144C4
Manufacturer:
ALTERA
0
Part Number:
EPM1270T144C4ES
Manufacturer:
ALTERA
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Part Number:
EPM1270T144C4N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EPM1270T144C4N
Manufacturer:
ALTERA
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Part Number:
EPM1270T144C4N
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Quantity:
20 000
Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
Table 5–21. UFM Block Internal Timing Microparameters (Part 2 of 3)
© August 2009 Altera Corporation
t
t
t
t
t
t
t
t
t
t
t
Symbol
DDS
DDH
DP
PB
BP
PP M X
AE
EB
BE
EPM X
DCO
Data register data in
setup to data register
clock
Data register data in
hold from data
register clock
Program signal to
data clock hold time
Maximum delay
between program
rising edge to UFM
busy signal rising
edge
Minimum delay
allowed from UFM
busy signal going low
to program signal
going low
Maximum length of
busy pulse during a
program
Minimum erase signal
to address clock hold
time
Maximum delay
between the erase
rising edge to the
UFM busy signal
rising edge
Minimum delay
allowed from the UFM
busy signal going low
to erase signal going
low
Maximum length of
busy pulse during an
erase
Delay from data
register clock to data
register output
Parameter
Min
–3 Speed
20
20
20
20
0
0
Grade
Max
960
100
960
500
5
MAX II / MAX IIG
Min
–4 Speed
20
20
20
20
0
0
Grade
Max
960
100
960
500
5
Min
–5 Speed
20
20
20
20
0
0
Grade
Max
960
100
960
500
5
Min Max Min Max Min Max
–6 Speed
20
20
20
20
0
0
Grade
960
100
960
500
5
–7 Speed
20
20
20
20
MAX IIZ
0
0
Grade
960
100
960
500
5
MAX II Device Handbook
–8 Speed
20
20
20
20
0
0
Grade
960
100
960
500
5
Unit
ms
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
5–15

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