EPM3512AFC256-10 Altera, EPM3512AFC256-10 Datasheet - Page 29
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EPM3512AFC256-10
Manufacturer Part Number
EPM3512AFC256-10
Description
IC MAX 3000A CPLD 512 256-FBGA
Manufacturer
Altera
Series
MAX® 3000Ar
Datasheet
1.EPM3032ATC44-10N.pdf
(46 pages)
Specifications of EPM3512AFC256-10
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
32
Number Of Macrocells
512
Number Of Gates
10000
Number Of I /o
208
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
256-FBGA
Voltage
3.0 V ~ 3.6 V
Memory Type
EEPROM
Number Of Logic Elements/cells
32
Family Name
MAX 3000A
# Macrocells
512
Number Of Usable Gates
10000
Frequency (max)
125MHz
Propagation Delay Time
10ns
Number Of Logic Blocks/elements
32
# I/os (max)
208
Operating Supply Voltage (typ)
3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
256
Package Type
FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-2279
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM3512AFC256-10
Manufacturer:
ALTERA
Quantity:
59
Company:
Part Number:
EPM3512AFC256-10
Manufacturer:
ALTERA
Quantity:
917
Part Number:
EPM3512AFC256-10
Manufacturer:
ALTERA
Quantity:
20 000
Company:
Part Number:
EPM3512AFC256-10N
Manufacturer:
ALTERA
Quantity:
13
Company:
Part Number:
EPM3512AFC256-10N
Manufacturer:
ALTERA
Quantity:
917
Part Number:
EPM3512AFC256-10N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
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Symbol
IN
IO
SEXP
PEXP
LAD
LAC
IOE
OD1
OD2
OD3
ZX1
ZX2
ZX3
XZ
SU
H
RD
COMB
IC
EN
GLOB
PRE
CLR
Table 17. EPM3032A Internal Timing Parameters (Part 1 of 2)
Input pad and buffer delay
I/O input pad and buffer
delay
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad
delay, slow slew rate = off
V
Output buffer and pad
delay, slow slew rate = off
V
Output buffer and pad
delay, slow slew rate = on
V
Output buffer enable delay,
slow slew rate = off
V
Output buffer enable delay,
slow slew rate = off
V
Output buffer enable delay,
slow slew rate = on
V
Output buffer disable delay C1 = 5 pF
Register setup time
Register hold time
Register delay
Combinatorial delay
Array clock delay
Register enable time
Global control delay
Register preset time
Register clear time
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
= 3.3 V
= 2.5 V
= 2.5 V or 3.3 V
= 3.3 V
= 2.5 V
= 2.5 V or 3.3 V
Parameter
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
Conditions
MAX 3000A Programmable Logic Device Family Data Sheet
Min
1.3
0.6
–4
Max
0.7
0.7
1.9
0.5
1.5
0.6
0.0
0.8
1.3
5.8
4.0
4.5
9.0
4.0
0.7
0.6
1.2
0.6
0.8
1.2
1.2
Note (1)
Speed Grade
Min
2.0
1.0
–7
Max
1.2
1.2
3.1
0.8
2.5
1.0
0.0
1.3
1.8
6.3
4.0
4.5
9.0
4.0
1.2
1.0
2.0
1.0
1.3
1.9
1.9
Min
2.8
1.3
–10
Max
10.0
1.5
1.0
3.3
5.0
1.3
2.5
1.9
2.6
1.5
4.0
1.2
0.0
1.8
2.3
6.8
5.0
5.5
1.5
1.2
2.6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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