EPM3512AFC256-10 Altera, EPM3512AFC256-10 Datasheet - Page 30
![IC MAX 3000A CPLD 512 256-FBGA](/photos/6/70/67063/544-256-fbga_sml.jpg)
EPM3512AFC256-10
Manufacturer Part Number
EPM3512AFC256-10
Description
IC MAX 3000A CPLD 512 256-FBGA
Manufacturer
Altera
Series
MAX® 3000Ar
Datasheet
1.EPM3032ATC44-10N.pdf
(46 pages)
Specifications of EPM3512AFC256-10
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
32
Number Of Macrocells
512
Number Of Gates
10000
Number Of I /o
208
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
256-FBGA
Voltage
3.0 V ~ 3.6 V
Memory Type
EEPROM
Number Of Logic Elements/cells
32
Family Name
MAX 3000A
# Macrocells
512
Number Of Usable Gates
10000
Frequency (max)
125MHz
Propagation Delay Time
10ns
Number Of Logic Blocks/elements
32
# I/os (max)
208
Operating Supply Voltage (typ)
3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
256
Package Type
FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-2279
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM3512AFC256-10
Manufacturer:
ALTERA
Quantity:
59
Company:
Part Number:
EPM3512AFC256-10
Manufacturer:
ALTERA
Quantity:
917
Part Number:
EPM3512AFC256-10
Manufacturer:
ALTERA
Quantity:
20 000
Company:
Part Number:
EPM3512AFC256-10N
Manufacturer:
ALTERA
Quantity:
13
Company:
Part Number:
EPM3512AFC256-10N
Manufacturer:
ALTERA
Quantity:
917
Part Number:
EPM3512AFC256-10N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
MAX 3000A Programmable Logic Device Family Data Sheet
30
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
t
f
Symbol
PIA
LPA
Symbol
PD1
PD2
SU
H
CO1
CH
CL
ASU
AH
ACO1
ACH
ACL
CPPW
CNT
CNT
ACNT
ACNT
Table 17. EPM3032A Internal Timing Parameters (Part 2 of 2)
Table 18. EPM3064A External Timing Parameters
PIA delay
Low–power adder
Input to non–registered
output
I/O input to non–registered
output
Global clock setup time
Global clock hold time
Global clock to output delay C1 = 35 pF
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
Array clock to output delay C1 = 35 pF
Array clock high time
Array clock low time
Minimum pulse width for
clear and preset
Minimum global clock
period
Maximum internal global
clock frequency
Minimum array clock period
Maximum internal array
clock frequency
Parameter
Parameter
(2)
(5)
C1 = 35 pF
C1 = 35 pF
(2)
(2)
(2)
(2)
(3)
(2)
(2),
(2)
(2),
Conditions
Conditions
(4)
(4)
(2)
(2)
(2)
Note (1)
222.2
222.2
Min
Min
2.8
0.0
1.0
2.0
2.0
1.6
0.3
1.0
2.0
2.0
2.0
–4
–4
Max
Max
4.5
4.5
3.1
4.3
4.5
4.5
0.9
2.5
Note (1)
135.1
135.1
Speed Grade
Speed Grade
Min
Min
4.7
0.0
1.0
3.0
3.0
2.6
0.4
1.0
3.0
3.0
3.0
–7
–7
Max
Max
1.5
4.0
7.5
7.5
5.1
7.2
7.4
7.4
100.0
100.0
Min
Min
6.2
0.0
1.0
4.0
4.0
3.6
0.6
1.0
4.0
4.0
4.0
Altera Corporation
–10
–10
Max
Max
10.0
10.0
10.0
10.0
2.1
5.0
7.0
9.6
MHz
MHz
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns