EPM7256SQC208-10N Altera, EPM7256SQC208-10N Datasheet - Page 29

• Manufacturer Part Number: EPM7256SQC208-10N
• Description: IC MAX 7000 CPLD 256 208-PQFP
• Manufacturer: Altera
• Series: MAX® 7000r

Specifications of EPM7256SQC208-10N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 4.75 V ~ 5.25 V
• Number Of Logic Elements/blocks: 16
• Number Of Macrocells: 256
• Number Of Gates: 5000
• Number Of I /o: 164
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Voltage: 5V
• Memory Type: EEPROM
• Number Of Logic Elements/cells: 16
• Family Name: MAX 7000S
• # Macrocells: 256
• Number Of Usable Gates: 5000
• Frequency (max): 125MHz
• Propagation Delay Time: 10ns
• Number Of Logic Blocks/elements: 16
• # I/os (max): 164
• Operating Supply Voltage (typ): 5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Figure 12. MAX 7000 Timing Model
Notes:
(1)
(2)
Altera Corporation
Only available in MAX 7000E and MAX 7000S devices.
Not available in 44-pin devices.
Delay
Input
t
I N
f
Delay
t
PIA
PIA
The timing characteristics of any signal path can be derived from the
timing model and parameters of a particular device. External timing
parameters, which represent pin-to-pin timing delays, can be calculated
as the sum of internal parameters.
relationship of internal and external delay parameters.
For more infomration, see
Timing).
Expander Delay
Internal Output
Global Control
Control Delay
Enable Delay
Logic Array
Register
Shared
Delay
t
Delay
t
t
t
t
t
t
GLOB
SEXP
LAD
LAC
I C
EN
IOE
(1)
MAX 7000 Programmable Logic Device Family Data Sheet
Expander Delay
Application Note 94 (Understanding MAX 7000
Parallel
t
PEXP
Input Delay
Figure 13
Fast
t
F I N
(1)
Register
t
t
t
t
t
t
t
t
Delay
SU
H
PRE
CLR
RD
COMB
FSU
FH
shows the internal timing
Output
Delay
t
t
t
t
t
t
t
OD1
OD2
OD3
XZ
Z
Z X2
Z X3
X1
(2)
(2)
(1)
Delay
I/O
t
I O
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