EPM7256SQC208-10N Altera, EPM7256SQC208-10N Datasheet - Page 37

• Manufacturer Part Number: EPM7256SQC208-10N
• Description: IC MAX 7000 CPLD 256 208-PQFP
• Manufacturer: Altera
• Series: MAX® 7000r

Specifications of EPM7256SQC208-10N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 4.75 V ~ 5.25 V
• Number Of Logic Elements/blocks: 16
• Number Of Macrocells: 256
• Number Of Gates: 5000
• Number Of I /o: 164
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Voltage: 5V
• Memory Type: EEPROM
• Number Of Logic Elements/cells: 16
• Family Name: MAX 7000S
• # Macrocells: 256
• Number Of Usable Gates: 5000
• Frequency (max): 125MHz
• Propagation Delay Time: 10ns
• Number Of Logic Blocks/elements: 16
• # I/os (max): 164
• Operating Supply Voltage (typ): 5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Altera Corporation
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
t
f
f
PD1
PD2
SU
H
FSU
FH
CO1
CH
CL
ASU
AH
ACO1
ACH
ACL
CPPW
ODH
CNT
CNT
ACNT
ACNT
MAX
Table 25. MAX 7000 & MAX 7000E External Timing Parameters
Input to non-registered output
I/O input to non-registered
output
Global clock setup time
Global clock hold time
Global clock setup time of fast
input
Global clock hold time of fast
input
Global clock to output delay
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
Array clock to output delay
Array clock high time
Array clock low time
Minimum pulse width for clear
and preset
Output data hold time after
clock
Minimum global clock period
Maximum internal global clock
frequency
Minimum array clock period
Maximum internal array clock
frequency
Maximum clock frequency
Parameter
C1 = 35 pF
C1 = 35 pF
(2)
(2)
C1 = 35 pF
C1 = 35 pF
(3)
C1 = 35 pF
(5)
(5)
(6)
Conditions
(4)
MAX 7000 Programmable Logic Device Family Data Sheet
Min
76.9
76.9
11.0
100
0.0
3.0
0.0
5.0
5.0
4.0
4.0
6.0
6.0
6.0
1.0
-15
Max
15.0
15.0
15.0
13.0
13.0
8.0
Note (1)
Speed Grade
Min
76.9
76.9
11.0
83.3
0.0
6.0
6.0
4.0
4.0
6.5
6.5
6.5
1.0
–
–
-15T
Max
15.0
15.0
15.0
13.0
13.0
8.0
Min
62.5
62.5
83.3
12.0
0.0
5.0
0.0
6.0
6.0
5.0
5.0
8.0
8.0
8.0
1.0
-20
Max
20.0
20.0
12.0
20.0
16.0
16.0
Unit
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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