EPM7256SQC208-10N Altera, EPM7256SQC208-10N Datasheet - Page 30

• Manufacturer Part Number: EPM7256SQC208-10N
• Description: IC MAX 7000 CPLD 256 208-PQFP
• Manufacturer: Altera
• Series: MAX® 7000r

Specifications of EPM7256SQC208-10N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 4.75 V ~ 5.25 V
• Number Of Logic Elements/blocks: 16
• Number Of Macrocells: 256
• Number Of Gates: 5000
• Number Of I /o: 164
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Voltage: 5V
• Memory Type: EEPROM
• Number Of Logic Elements/cells: 16
• Family Name: MAX 7000S
• # Macrocells: 256
• Number Of Usable Gates: 5000
• Frequency (max): 125MHz
• Propagation Delay Time: 10ns
• Number Of Logic Blocks/elements: 16
• # I/os (max): 164
• Operating Supply Voltage (typ): 5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MAX 7000 Programmable Logic Device Family Data Sheet
Figure 13. Switching Waveforms
30
t
Inputs are driven at 3 V
for a logic high and 0 V
for a logic low. All timing
characteristics are
measured at 1.5 V.
R
& t
F
< 3 ns.
(Logic Array Output)
Parallel Expander
Shared Expander
Register Output
Input or I/O Pin
Register to PIA
Data or Enable
Clock into PIA
to Logic Array
Global Clock
Logic Array
Logic Array
Logic Array
Logic Array
Output Pin
at Register
PIA Delay
Clock into
Data from
Input Pin
Clock Pin
Register
Clock at
I/O Pin
Output
Global
Delay
Delay
to Pin
Input
Combinatorial Mode
Global Clock Mode
Array Clock Mode
t
t
R
R
t
t
IN
t
t
SU
IN
IO
t
t
ACH
CH
t
t
t
t
H
t
PIA
IN
GLOB
IO
t
RD
t
t
IC
SU
t
PIA
t
t
ACL
t
CL
SEXP
t
H
t
PIA
t
OD
t
LAC
, t
LAD
t
PEXP
t
t
F
F
t
COMB
Altera Corporation
t
CLR
, t
PRE
t
OD
t
OD
t
PIA