EPM7256AETI144-7N Altera, EPM7256AETI144-7N Datasheet - Page 32
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EPM7256AETI144-7N
Manufacturer Part Number
EPM7256AETI144-7N
Description
IC MAX 7000 CPLD 256 144-TQFP
Manufacturer
Altera
Series
MAX® 7000Ar
Datasheet
1.EPM7032AELC44-10N.pdf
(64 pages)
Specifications of EPM7256AETI144-7N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
16
Number Of Macrocells
256
Number Of Gates
5000
Number Of I /o
120
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
144-TQFP, 144-VQFP
Voltage
3.3V
Memory Type
EEPROM
Number Of Logic Elements/cells
16
Family Name
MAX 7000A
# Macrocells
256
Number Of Usable Gates
5000
Frequency (max)
166.67MHz
Propagation Delay Time
7.5ns
Number Of Logic Blocks/elements
16
# I/os (max)
120
Operating Supply Voltage (typ)
3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
144
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2063
EPM7256AETI144-7N
EPM7256AETI144-7N
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Part Number
Manufacturer
Quantity
Price
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MAX 7000A Programmable Logic Device Data Sheet
Figure 11. MAX 7000A Timing Model
32
Delay
f
Input
t
I N
Delay
PIA
t
PIA
The timing characteristics of any signal path can be derived from the
timing model and parameters of a particular device. External timing
parameters, which represent pin-to-pin timing delays, can be calculated
as the sum of internal parameters.
between internal and external delay parameters.
See
information.
Application Note 94 (Understanding MAX 7000 Timing)
Expander Delay
Internal Output
Global Control
Control Delay
Enable Delay
Logic Array
Register
Shared
Delay
Delay
t
t
t
t
t
t
t
GLOB
SEXP
LAD
LAC
I C
EN
IOE
Expander Delay
Parallel
t
PEXP
Figure 12
Input Delay
Fast
t
F I N
Register
t
t
t
t
t
t
t
t
shows the timing relationship
Delay
SU
H
PRE
CLR
RD
COMB
FSU
FH
Altera Corporation
Output
Delay
t
t
t
t
t
t
t
OD1
OD2
OD3
XZ
Z
Z X2
Z X3
X1
for more
Delay
I/O
t
I O