EPM7256AETI144-7N Altera, EPM7256AETI144-7N Datasheet - Page 9

• Manufacturer Part Number: EPM7256AETI144-7N
• Description: IC MAX 7000 CPLD 256 144-TQFP
• Manufacturer: Altera
• Series: MAX® 7000Ar

Specifications of EPM7256AETI144-7N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 3 V ~ 3.6 V
• Number Of Logic Elements/blocks: 16
• Number Of Macrocells: 256
• Number Of Gates: 5000
• Number Of I /o: 120
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-TQFP, 144-VQFP
• Voltage: 3.3V
• Memory Type: EEPROM
• Number Of Logic Elements/cells: 16
• Family Name: MAX 7000A
• # Macrocells: 256
• Number Of Usable Gates: 5000
• Frequency (max): 166.67MHz
• Propagation Delay Time: 7.5ns
• Number Of Logic Blocks/elements: 16
• # I/os (max): 120
• Operating Supply Voltage (typ): 3.3V
• In System Programmable: Yes
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2063; EPM7256AETI144-7N

Altera Corporation
For registered functions, each macrocell flipflop can be individually
programmed to implement D, T, JK, or SR operation with programmable
clock control. The flipflop can be bypassed for combinatorial operation.
During design entry, the designer specifies the desired flipflop type; the
Altera software then selects the most efficient flipflop operation for each
registered function to optimize resource utilization.
Each programmable register can be clocked in three different modes:
Two global clock signals are available in MAX 7000A devices. As shown
in
either of the global clock pins, GCLK1 or GCLK2.
Each register also supports asynchronous preset and clear functions. As
shown in
to control these operations. Although the product-term-driven preset and
clear from the register are active high, active-low control can be obtained
by inverting the signal within the logic array. In addition, each register
clear function can be individually driven by the active-low dedicated
global clear pin (GCLRn). Upon power-up, each register in a MAX 7000AE
device may be set to either a high or low state. This power-up state is
specified at design entry. Upon power-up, each register in EPM7128A and
EPM7256A devices are set to a low state.
All MAX 7000A I/O pins have a fast input path to a macrocell register.
This dedicated path allows a signal to bypass the PIA and combinatorial
logic and be clocked to an input D flipflop with an extremely fast (as low
as 2.5 ns) input setup time.
Figure
Global clock signal. This mode achieves the fastest clock-to-output
performance.
Global clock signal enabled by an active-high clock enable. A clock
enable is generated by a product term. This mode provides an enable
on each flipflop while still achieving the fast clock-to-output
performance of the global clock.
Array clock implemented with a product term. In this mode, the
flipflop can be clocked by signals from buried macrocells or I/O pins.
1, these global clock signals can be the true or the complement of
Figure
2, the product-term select matrix allocates product terms
MAX 7000A Programmable Logic Device Data Sheet
9