EPM7256AETI144-7N Altera, EPM7256AETI144-7N Datasheet - Page 46
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EPM7256AETI144-7N
Manufacturer Part Number
EPM7256AETI144-7N
Description
IC MAX 7000 CPLD 256 144-TQFP
Manufacturer
Altera
Series
MAX® 7000Ar
Datasheet
1.EPM7032AELC44-10N.pdf
(64 pages)
Specifications of EPM7256AETI144-7N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
16
Number Of Macrocells
256
Number Of Gates
5000
Number Of I /o
120
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
144-TQFP, 144-VQFP
Voltage
3.3V
Memory Type
EEPROM
Number Of Logic Elements/cells
16
Family Name
MAX 7000A
# Macrocells
256
Number Of Usable Gates
5000
Frequency (max)
166.67MHz
Propagation Delay Time
7.5ns
Number Of Logic Blocks/elements
16
# I/os (max)
120
Operating Supply Voltage (typ)
3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
144
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2063
EPM7256AETI144-7N
EPM7256AETI144-7N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM7256AETI144-7N
Manufacturer:
SPANSION
Quantity:
1 001
Company:
Part Number:
EPM7256AETI144-7N
Manufacturer:
ALTERA
Quantity:
40
Company:
Part Number:
EPM7256AETI144-7N
Manufacturer:
ALTERA
Quantity:
3 530
MAX 7000A Programmable Logic Device Data Sheet
46
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
t
f
Symbol
PD1
PD2
SU
H
FSU
FH
CO1
CH
CL
ASU
AH
ACO1
ACH
ACL
CPPW
CNT
CNT
ACNT
ACNT
Table 25. EPM7512AE External Timing Parameters
Input to non-
registered output
I/O input to non-
registered output
Global clock setup
time
Global clock hold time
Global clock setup
time of fast input
Global clock hold time
of fast input
Global clock to output
delay
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
Array clock to output
delay
Array clock high time
Array clock low time
Minimum pulse width
for clear and preset
Minimum global clock
period
Maximum internal
global clock frequency
Minimum array clock
period
Maximum internal
array clock frequency
Parameter
C1 = 35 pF
(2)
C1 = 35 pF
(2)
(2)
(2)
C1 = 35 pF
(2)
(2)
C1 = 35 pF
(2)
(3)
(2)
(2),
(2)
(2),
Conditions
(4)
(4)
116.3
116.3
Min
3.0
5.6
0.0
3.0
0.0
1.0
3.0
2.5
0.2
1.0
3.0
3.0
3.0
-7
Note (1)
Max
7.5
7.5
4.7
7.8
8.6
8.6
87.0
87.0
Speed Grade
Min
7.6
0.0
3.0
0.0
1.0
4.0
4.0
3.5
0.3
1.0
4.0
4.0
4.0
-10
Max
10.0
10.0
10.4
11.5
11.5
6.3
71.9
71.9
Min
Altera Corporation
9.1
0.0
3.0
0.0
1.0
5.0
5.0
4.1
0.4
1.0
5.0
5.0
5.0
-12
Max
12.0
12.0
12.5
13.9
13.9
7.5
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns