CY39200V388-125MGC Cypress Semiconductor Corp, CY39200V388-125MGC Datasheet - Page 17

• Manufacturer Part Number: CY39200V388-125MGC
• Description: IC CPLD 200K GATE 388-BGA
• Manufacturer: Cypress Semiconductor Corp
• Series: Delta 39K™ ISR™r

Specifications of CY39200V388-125MGC

• Programmable Type: In-System Reprogrammable™ (ISR™) Flash
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 2.5V, 3.3V
• Number Of Macrocells: 3072
• Number Of Gates: 288000
• Number Of I /o: 294
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 388-BGA
• Voltage: 1.8V, 2.5V, 3.3V
• Memory Type: FLASH
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of Logic Elements/cells: -
• Other names: 428-1297

Capacitance
DC Characteristics (I/O)
Notes:
Configuration Parameters
Document #: 38-03039 Rev. *D
10. See “Power-up Sequence Requirements” below for V
11. 25 resistor terminated to termination voltage of 1.5V.
LVTTL –2mA
LVTTL –4mA
LVTTL –6mA
LVTTL –8mA
LVTTL –12mA
LVTTL –16mA
LVTTL –24mA
LVCMOS
LVCMOS3
LVCMOS2
LVCMOS18
3.3V PCI
GTL+
SSTL3 I
SSTL3 II
SSTL2 I
SSTL2 II
HSTL I
HSTL II
HSTL III
HSTL IV
8.
9.
I/O Standards
C
C
C
t
RECONFIG
I/O
CLK
PCI
PCI spec (rev 2.2) requires the IDSEL pin to have capacitance less than or equal to 8 pF. Delta39K Pin Tables starting from page 51, identify all the I/O pins in
a given package, which can be used as IDSEL in a PCI design. All other I/O pins meet the PCI requirement of capacitance less than or equal to 10 pf.
The number of I/Os which can be used in each I/O bank depends on the type of I/O standards and the number of V
to the application note titled “Delta39K and Quantum38K I/O Standards and Configurations” for details.
• The source current limit per I/O bank per Vccio pin is 165 mA.
• The sink current limit per I/O bank per GND pin is 230 mA.
Parameter
Parameter
V
1.25
1.25
0.75
0.75
N/A
1.0
1.5
1.5
0.9
0.9
(V)
REF
Input/Output Capacitance
Clock Signal Capacitance
PCI Compliant
V
CCIO
(V)
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.0
2.5
1.8
3.3
[10]
3.3
3.3
2.5
2.5
1.5
1.5
1.5
1.5
[9]
–15.2 mA V
–0.1 mA
–0.1 mA
–0.1 mA
–1.0 mA
–2.0 mA
–0.5 mA
–7.6 mA V
@ I
–12 mA
–16 mA
–24 mA
–16 mA
–16 mA
– 2 mA
Reconfig pin LOW time before it goes HIGH
Description
–2 mA
–4 mA
–6 mA
–8 mA
–8 mA
–8 mA
–8 mA
–8 mA
OH
PRELIMINARY
[8]
=
Capacitance
V
OH
V
V
V
V
V
V
V
V
V
V
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
(V)
0.9V
CCIO
OH
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.1
2.0
1.7
(min.)
– 0.45v
– 0.62v
– 0.43v 15.2 mA
requirement.
CCIO
– 0.2v
– 0.2v
– 1.1v
– 0.9v
– 0.4v
– 0.4v
– 0.4v
– 0.4v
V
V
V
36 mA
in
in
in
@ I
0.1 mA
0.1 mA
1.0 mA
2.0 mA
2.0 mA
1.5 mA
7.6 mA
12 mA
16 mA
24 mA
0.1mA
16 mA
16 mA
24 mA
48 mA
2 mA
4 mA
6 mA
8 mA
8 mA
8 mA
= V
= V
= V
Description
OL
CCIO
CCIO
CCIO
V
[11]
=
OL
Test Conditions
(V)
0.1V
@ f = 1 MHz 25°C
@ f = 1 MHz 25°C
@ f = 1 MHz 25°C
(max.)
0.45
0.54
0.35
V
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.2
0.2
0.2
0.4
0.7
0.6
0.7
0.5
0.4
0.4
0.4
0.4
OL
CCIO
V
V
V
V
V
V
V
V
V
0.65V
0.5V
REF
REF
REF
REF
REF
REF
REF
REF
REF
2.0 V
2.0 V
2.0 V
2.0 V
2.0 V
2.0 V
2.0 V
2.0 V
2.0 V
1.7 V
Min.
+ 0.18 V
+ 0.18 V
CCIO
+ 0.2
+ 0.2 V
+ 0.2 V
+ 0.1 V
+ 0.1 V
+ 0.1 V
+ 0.1 V
CCIO
V
IH
CCIO
(V)
V
V
V
V
V
V
V
V
V
V
V
V
Delta39K™ ISR™
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
and GND pins being used. Please refer
Max.
Min.
5
+ 0.3 –0.3V
+ 0.3 –0.3V
+ 0.3 –0.3V
+ 0.3 –0.3V
+ 0.3 –0.3V
+ 0.3 –0.3V
+ 0.3 –0.3V
+ 0.3 –0.3V
+ 0.3 –0.3V
+ 0.3 –0.3V
+ 0.3 –0.3V 0.35V
+ 0.5 –0.5V
+ 0.3 –0.3V V
+ 0.3 –0.3V V
+ 0.3 –0.3V V
+ 0.3 –0.3V V
+ 0.3 –0.3V V
+ 0.3 –0.3V V
+ 0.3 –0.3V V
+ 0.3 –0.3V V
CPLD Family
Min.
200
Min.
Max.
10
12
8
Page 17 of 91
V
IL
V
0.3V
REF
REF
REF
REF
REF
REF
REF
REF
REF
(V)
Max.
0.8V
0.8V
0.8V
0.8V
0.8V
0.8V
0.8V
0.8V
0.8V
0.7V
Unit
Unit
ns
– 0.18
– 0.18
pF
pF
pF
CCIO
– 0.2
– 0.2
– 0.2
– 0.1
– 0.1
– 0.1
– 0.1
CCIO