DSPB56725AF Freescale Semiconductor, DSPB56725AF Datasheet - Page 15
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DSPB56725AF
Manufacturer Part Number
DSPB56725AF
Description
DSP 24BIT AUD 250MHZ 80-LQFP
Manufacturer
Freescale Semiconductor
Series
Symphony™r
Type
Audio Processorr
Specifications of DSPB56725AF
Interface
Host Interface, I²C, SAI, SPI
Clock Rate
250MHz
Non-volatile Memory
External
On-chip Ram
112kB
Voltage - I/o
3.30V
Voltage - Core
1.20V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
80-LQFP
Processor Series
DSP567xx
Core
56300
Leaded Process Compatible
Yes
Rohs Compliant
Yes
Peak Reflow Compatible (260 C)
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPB56725AF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
2.9
Table 7
Freescale Semiconductor
No.
10
11
13
14
15
16
17
18
19
20
21
shows the reset, stop, mode select, and interrupt timing.
Delay from RESET assertion to all pins at reset value
Required RESET duration
Syn reset deassert delay time
Mode select setup time
Mode select hold time
Minimum edge-triggered interrupt request assertion width
Minimum edge-triggered interrupt request deassertion width
Delay from interrupt trigger to interrupt code execution
Duration of level sensitive IRQA assertion to ensure interrupt service
(when exiting Stop)
Interrupt Requests Rate
• Power on, external clock generator, PLL disabled
• Power on, external clock generator, PLL enabled
• Minimum
• Maximum (PLL enabled)
• PLL is active during Stop and Stop delay is enabled (OMR Bit 6 = 0)
• PLL is active during Stop and Stop delay is not enabled (OMR Bit 6 =
• PLL is not active during Stop and Stop delay is enabled (OMR Bit 6 =
• PLL is not active during Stop and Stop delay is not enabled (OMR Bit
• Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to
• ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1, Timer, Timer_1
• DMA
• IRQ, NMI (edge trigger)
• IRQ (level trigger)
Reset, Stop, Mode Select, and Interrupt Timing
1)
0)
6 = 1)
general-purpose transfer output valid caused by first interrupt
instruction execution
Table 7. Reset, Stop, Mode Select, and Interrupt Timing Parameters
Symphony
1, 2, 3
1
1
4
Characteristics
™
DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5
3
(128 Kbytes × T
(128 Kbytes × T
(25 × T
(2 x T
10 × T
Expression
10 × T
25 × T
12 × T
12 × T
2 × T
2 × T
2 × T
T
8 × T
8 × T
C
C
LOCK
—
) + T
—
—
—
—
) + T
C
C + 4
+ 3.8
C
C
C
C
C
C
C
C
LOCK
LOCK
C
C)
) +
10.0
Min
200
655
125
855
200
10
10
10
12
54
—
—
—
—
—
—
7
4
Max
53.8
60.0
40.0
40.0
60.0
11
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
us
ns
ns
ns
ns
ns
μs
ns
μs
μs
ns
ns
ns
ns
ns
15