DSPB56725AF Freescale Semiconductor, DSPB56725AF Datasheet - Page 29
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DSPB56725AF
Manufacturer Part Number
DSPB56725AF
Description
DSP 24BIT AUD 250MHZ 80-LQFP
Manufacturer
Freescale Semiconductor
Series
Symphony™r
Type
Audio Processorr
Specifications of DSPB56725AF
Interface
Host Interface, I²C, SAI, SPI
Clock Rate
250MHz
Non-volatile Memory
External
On-chip Ram
112kB
Voltage - I/o
3.30V
Voltage - Core
1.20V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
80-LQFP
Processor Series
DSP567xx
Core
56300
Leaded Process Compatible
Yes
Rohs Compliant
Yes
Peak Reflow Compatible (260 C)
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPB56725AF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Freescale Semiconductor
Notes:
1. V
2. i ck = internal clock
3. bl = bit length
4. SCKT(SCKT pin) = transmit clock
5. For the internal clock, the external clock cycle is defined by Tc and the ESAI control register.
6. The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync
7. Periodically sampled and not 100% tested.
8. ESAI_1, ESAI_2, ESAI_3 specs match those of ESAI.
No.
92
93
94
95
96
97
x ck = external clock
i ck a = internal clock, asynchronous mode
(Asynchronous implies that SCKT and SCKR are two different clocks.)
i ck s = internal clock, synchronous mode
(Synchronous implies that SCKT and SCKR are the same clock.)
wl = word length
wr = word length relative
SCKR(SCKR pin) = receive clock
FST(FST pin) = transmit frame sync
FSR(FSR pin) = receive frame sync
HCKT(HCKT pin) = transmit high frequency clock
HCKR(HCKR pin) = receive high frequency clock
signal waveform, but spreads from one serial clock before first bit clock (same as bit length frame sync signal), until the one
before last bit clock of the first word in frame.
CORE_VDD
FST input (wl) to data out enable from high impedance
FST input (wl) to transmitter #0 drive enable assertion
Flag output valid after SCKT rising edge
HCKR/HCKT clock cycle
HCKT input rising edge to SCKT output
HCKR input rising edge to SCKR output
= 1.00 ± 0.10 V; T
Table 10. Enhanced Serial Audio Interface Timing Parameters (Continued)
Characteristics
Symphony
J
= –40°C to 100°C; C
™
DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5
1, 3, 4
L
= 50 pF.
Symbol
—
—
—
—
—
—
Expression
2 × T
—
—
—
—
—
C
5
Min
10
—
—
—
—
—
—
Max
21.0
14.0
14.0
18.0
18.0
9.0
—
Condition
x ck
i ck
—
—
—
—
—
2
Unit
ns
ns
ns
ns
ns
ns
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