KMSC8122TMP6400 Freescale Semiconductor, KMSC8122TMP6400 Datasheet - Page 19

• Manufacturer Part Number: KMSC8122TMP6400
• Description: DSP 16BIT QUAD CORE 431-FCPBGA
• Manufacturer: Freescale Semiconductor
• Series: MSC81xx StarCorer
• Type: SC140 Corer

Specifications of KMSC8122TMP6400

• Interface: DSI, Ethernet, RS-232
• Clock Rate: 400MHz
• Non-volatile Memory: External
• On-chip Ram: 1.436MB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 431-FCPBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

2.5.4
The MSC8122 has several inputs to the reset logic:
All MSC8122 reset sources are fed into the reset controller, which takes different actions depending on the source of the reset.
The reset status register indicates the most recent sources to cause a reset. Table 10 describes the reset sources.
Freescale Semiconductor
Power-on reset
(PORESET)
External hard
reset (HRESET)
External soft reset
(SRESET)
Software
watchdog reset
Bus monitor reset
Host reset
command through
the TAP
Phase jitter between BCLK and CLKIN
CLKIN frequency
CLKIN slope
CLKIN period jitter
CLKIN jitter spectrum
PLL input clock (after predivider)
PLL output frequency (VCO output)
•
•
•
CLKOUT frequency jitter
CLKOUT phase jitter
Notes:
300 MHz core
400 MHz core
500 MHz core
•
•
•
•
•
•
Name
Power-on reset (
External hard reset (
External soft reset (
Software watchdog reset
Bus monitor reset
Host reset command through JTAG
1.
2.
Reset Timing
Peak-to-peak.
Not tested. Guaranteed by design.
1
1
with CLKIN phase jitter of ±100 ps.
Input/ Output
Input/ Output
Direction
1
Internal
Internal
Internal
Input
PORESET
Characteristic
SRESET
HRESET
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
)
Initiates the power-on reset flow that resets the MSC8122 and configures various attributes of the
MSC8122. On PORESET, the entire MSC8122 device is reset. SPLL states is reset, HRESET and
SRESET are driven, the SC140 extended cores are reset, and system configuration is sampled. The
clock mode (MODCK bits), reset configuration mode, boot mode, Chip ID, and use of either a DSI 64
bits port or a System Bus 64 bits port are configured only when PORESET is asserted.
Initiates the hard reset flow that configures various attributes of the MSC8122. While HRESET is
asserted, SRESET is also asserted. HRESET is an open-drain pin. Upon hard reset, HRESET and
SRESET are driven, the SC140 extended cores are reset, and system configuration is sampled. The
most configurable features are reconfigured. These features are defined in the 32-bit hard reset
configuration word described in Hard Reset Configuration Word section of the Reset chapter in the
MSC8122 Reference Manual.
Initiates the soft reset flow. The MSC8122 detects an external assertion of SRESET only if it occurs
while the MSC8122 is not asserting reset. SRESET is an open-drain pin. Upon soft reset, SRESET is
driven, the SC140 extended cores are reset, and system configuration is maintained.
When the MSC8122 watchdog count reaches zero, a software watchdog reset is signalled. The
enabled software watchdog event then generates an internal hard reset sequence.
When the MSC8122 bus monitor count reaches zero, a bus monitor hard reset is asserted. The
enabled bus monitor event then generates an internal hard reset sequence.
When a host reset command is written through the Test Access Port (TAP), the TAP logic asserts the
soft reset signal and an internal soft reset sequence is generated.
)
)
Table 9. System Clock Parameters
Table 10. Reset Sources
Description
Min
150
800
20
20
—
—
—
—
—
see Table 8
Max
1200
1600
2000
150
100
200
500
0.3
—
3
Electrical Characteristics
Unit
MHz
MHz
MHz
MHz
MHz
MHz
KHz
ns
ns
ps
ps
ps
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