KMSC8122TMP6400 Freescale Semiconductor, KMSC8122TMP6400 Datasheet - Page 23

• Manufacturer Part Number: KMSC8122TMP6400
• Description: DSP 16BIT QUAD CORE 431-FCPBGA
• Manufacturer: Freescale Semiconductor
• Series: MSC81xx StarCorer
• Type: SC140 Corer

Specifications of KMSC8122TMP6400

• Interface: DSI, Ethernet, RS-232
• Clock Rate: 400MHz
• Non-volatile Memory: External
• On-chip Ram: 1.436MB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 431-FCPBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The UPM machine and GPCM machine outputs change on the internal tick selected by the memory controller configuration.
The AC timing specifications are relative to the internal tick. SDRAM machine outputs change only on the
Freescale Semiconductor
Notes:
No.
11a
11b
11d
15a
15b
11c
13
14
10
12
16
17
18
1
1
Hold time for all signals after the 50% level of the REFCLK rising edge
ARTRY/ABB set-up time before the 50% level of the REFCLK rising
edge
DBG/DBB/BG/BR/TC set-up time before the 50% level of the REFCLK
rising edge
AACK set-up time before the 50% level of the REFCLK rising edge
TA/TEA/PSDVAL set-up time before the 50% level of the REFCLK
rising edge
•
•
Data bus set-up time before REFCLK rising edge in Normal mode
•
•
Data bus set-up time before the 50% level of the REFCLK rising edge
in ECC and PARITY modes
•
•
DP set-up time before the 50% level of the REFCLK rising edge
•
•
TS and Address bus set-up time before the 50% level of the REFCLK
rising edge
•
•
Address attributes: TT/TBST/TSZ/GBL set-up time before the 50%
level of the REFCLK rising edge
•
•
PUPMWAIT signal set-up time before the 50% level of the REFCLK
rising edge
IRQx setup time before the 50% level; of the REFCLK rising edge
IRQx minimum pulse width
1.
2.
3.
Data-pipeline mode
Non-pipeline mode
Data-pipeline mode
Non-pipeline mode
Data-pipeline mode
Non-pipeline mode
Data-pipeline mode
Non-pipeline mode
Extra cycle mode (SIUBCR[EXDD] = 0)
No extra cycle mode (SIUBCR[EXDD] = 1)
Extra cycle mode (SIUBCR[EXDD] = 0)
No extra cycle mode (SIUBCR[EXDD] = 1)
Timings specifications 13 and 14 in non-pipeline mode are more restrictive than MSC8102 timings.
Values are measured from the 50% TTL transition level relative to the 50% level of the REFCLK rising edge.
Guaranteed by design.
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Characteristic
3
Table 14. AC Timing for SIU Inputs
3
T
1.1 V
REFCLK
100/
6.0 +
133
0.5
3.1
3.6
3.0
3.5
4.4
1.9
4.2
2.0
8.2
2.0
7.9
4.2
5.5
3.7
4.8
3.7
4.0
Ref = CLKIN
Value for Bus Speed in MHz
T
1.2 V
REFCLK
6.0 +
133
0.5
3.0
3.3
2.9
3.4
4.0
1.8
4.0
2.0
7.3
2.0
6.1
3.8
5.0
3.5
4.4
3.7
4.0
T
1.2 V
REFCLK
6.0 +
166
0.5
3.0
3.3
2.9
3.4
4.0
1.7
4.0
2.0
7.3
2.0
6.1
3.8
5.0
3.5
4.4
3.7
4.0
Electrical Characteristics
Ref = CLKOUT
6.0 + T
REFCLK
1.2 V
133
0.5
3.0
3.3
2.9
3.4
4.0
1.8
4.0
2.0
7.3
2.0
6.1
3.8
5.0
3.5
4.4
3.7
4.0
REFCLK
rising edge.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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