EP1C3T100I7N Altera, EP1C3T100I7N Datasheet - Page 40

• Manufacturer Part Number: EP1C3T100I7N
• Description: IC CYCLONE FPGA 2910 LE 100-TQFP
• Manufacturer: Altera
• Series: Cyclone®r

Specifications of EP1C3T100I7N

• Number Of Logic Elements/cells: 2910
• Number Of Labs/clbs: 291
• Total Ram Bits: 59904
• Number Of I /o: 65
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 100-TQFP, 100-VQFP
• Family Name: Cyclone®
• Number Of Logic Blocks/elements: 2910
• # I/os (max): 65
• Frequency (max): 320.1MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 2910
• Ram Bits: 59904
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1663

Cyclone Device Handbook, Volume 1
Figure 2–26. Cyclone PLL Global Clock Connections
Notes to
(1)
(2)
(3)
(4)
2–34
Preliminary
PLL1_OUT (3), (4)
PLL Counter
Output
Dedicated
Clock Input
Pins
Table 2–7. Global Clock Network Sources (Part 1 of 2)
PLL 1 supports one single-ended or LVDS input via pins CLK0 and CLK1.
PLL2 supports one single-ended or LVDS input via pins CLK2 and CLK3.
PLL1_OUT and PLL2_OUT support single-ended or LVDS output. If external output is not required, these pins are
available as regular user I/O pins.
The EP1C3 device in the 100-pin TQFP package does not support external clock output. The EP1C6 device in the
144-pin TQFP package does not support external clock output from PLL2.
CLK1 (1)
Figure
CLK0
Source
2–26:
PLL1 G0
PLL1 G1
PLL2 G0
PLL2 G1
CLK0
CLK1
CLK2
CLK3
(2)
(2)
(1)
(1)
Figure 2–26
Table 2–7
devices.
PLL1
GCLK0
v
v
—
—
—
—
—
—
g0
g1
e
shows the global clock network sources available in Cyclone
GCLK1
G0
shows the PLL global clock connections.
v
v
—
—
—
—
—
—
G1
G2
G3
GCLK2
v
v
—
—
—
—
—
—
G4
G5
GCLK3
G6
v
v
—
—
—
—
—
—
G7
GCLK4
g0
g1
e
v
v
—
—
—
—
—
—
PLL2
GCLK5
v
v
—
—
—
—
—
—
Altera Corporation
GCLK6
v
v
—
—
—
—
—
—
CLK2
CLK3 (2)
PLL2_OUT (3), (4)
May 2008
GCLK7
v
v
—
—
—
—
—
—