EP1C3T100I7N Altera, EP1C3T100I7N Datasheet - Page 83

• Manufacturer Part Number: EP1C3T100I7N
• Description: IC CYCLONE FPGA 2910 LE 100-TQFP
• Manufacturer: Altera
• Series: Cyclone®r

Specifications of EP1C3T100I7N

• Number Of Logic Elements/cells: 2910
• Number Of Labs/clbs: 291
• Total Ram Bits: 59904
• Number Of I /o: 65
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 100-TQFP, 100-VQFP
• Family Name: Cyclone®
• Number Of Logic Blocks/elements: 2910
• # I/os (max): 65
• Frequency (max): 320.1MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 2910
• Ram Bits: 59904
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1663

Figure 4–1. Dual-Port RAM Timing Microparameter Waveform
Altera Corporation
May 2008
unreg_data-out
reg_data-out
wraddress
rdaddress
rdclock
data-in
wrclock
wren
rden
doutn-2
an-1
din-1
t
t
DATASU
WERESU
doutn-1
bn
t
DATAH
din
an
Figure 4–1
shown in
t
t
t
R4
C4
LOCAL
Table 4–24. Routing Delay Internal Timing Microparameter Descriptions
t
doutn-1
WEREH
doutn
Symbol
a0
b0
Table
shows the memory waveforms for the M4K timing parameters
t
t
DATACO1
WEREH
4–23.
t
DATACO2
Delay for an R4 line with average loading; covers a distance
of four LAB columns
Delay for an C4 line with average loading; covers a distance
of four LAB rows
Local interconnect delay
a1
t
RC
doutn
dout0
a2
b1
t
t
WADDRSU
a3
WERESU
Parameter
dout0
din4
a4
b2
t
WADDRH
din5
a5
Timing Model
Preliminary
b3
din6
a6
4–13