EP3C55F484C8N Altera, EP3C55F484C8N Datasheet - Page 190

• Manufacturer Part Number: EP3C55F484C8N
• Description: IC CYCLONE III FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C55F484C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2396160
• Number Of I /o: 327
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 327
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 3491
• Family Type: Cyclone III
• No. Of I/o's: 327
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2510

9–30
Cyclone III Device Handbook, Volume 1
As shown in
target devices are connected together with external pull-up resistors. These pins are
open-drain bidirectional pins on the devices. When the first device asserts nCEO (after
receiving all its configuration data), it releases its CONF_DONE pin. However, the
subsequent devices in the chain keep this shared CONF_DONE line low until they
receive their configuration data. When all target devices in the chain receive their
configuration data and release CONF_DONE, the pull-up resistor drives a high level on
this line and all devices simultaneously enter initialization mode.
Guidelines for Connecting Parallel Flash to Cyclone III Devices for the AP Interface
For the single- and multi-device AP configuration, the board trace length and loading
between the supported parallel flash and Cyclone III devices must follow the
recommendations listed in
configuration with multiple bus masters.
Table 9–12. Maximum Trace Length and Loading for the AP Configuration
Configuring With Multiple Bus Masters
Similar to the AS configuration scheme, the AP configuration scheme supports
multiple bus masters for the parallel flash. For another master to take control of the
AP configuration bus, the master must assert nCONFIG low for at least 500 ns to reset
the master Cyclone III device and override the weak 10 kΩ pull-down resistor on the
nCE pin. This resets the master Cyclone III device and causes it to tri-state its AP
configuration bus. The other master then takes control of the AP configuration bus.
After the other master is done, it releases the AP configuration bus, then releases the
nCE pin, and finally pulses nCONFIG low to restart the configuration.
In the AP configuration scheme, multiple masters share the parallel flash. Similar to
the AS configuration scheme, the bus control is negotiated by the nCE pin.
DCLK
DATA[15..0]
PADD[23..0]
nRESET
Flash_nCE
nOE
nAVD
nWE
I/O
Note to
(1) The AP configuration ignores the WAIT signal from the flash during configuration mode. However, if you are
Cyclone III AP Pins
accessing flash during user mode with user logic, you can optionally use the normal I/O to monitor the WAIT signal
from the Numonyx P30 or P33 flash.
(1)
Table
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
9–12:
Figure 9–9
and
Maximum Board Trace Length from the
Cyclone III Device to the Flash Device
Table
Figure
9–12. These recommendations also apply to an AP
9–10, the nSTATUS and CONF_DONE pins on all
(Inches)
6
6
6
6
6
6
6
6
6
© December 2009 Altera Corporation
Maximum Board Load (pF)
Configuration Features
15
30
30
30
30
30
30
30
30