EP3C55F484C8N Altera, EP3C55F484C8N Datasheet - Page 30

• Manufacturer Part Number: EP3C55F484C8N
• Description: IC CYCLONE III FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C55F484C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2396160
• Number Of I /o: 327
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 327
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 3491
• Family Type: Cyclone III
• No. Of I/o's: 327
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2510

2–2
Figure 2–1. Cyclone III Device Family LEs
LE Features
Cyclone III Device Handbook, Volume 1
data 1
data 2
data 3
data 4
Figure 2–1
You can configure the programmable register of each LE for D, T, JK, or SR flipflop
operation. Each register has data, clock, clock enable, and clear inputs. Signals that
use the global clock network, general-purpose I/O pins, or any internal logic can
drive the clock and clear control signals of the register. Either general-purpose I/O
pins or the internal logic can drive the clock enable. For combinational functions, the
LUT output bypasses the register and drives directly to the LE outputs.
Each LE has three outputs that drive the local, row, and column routing resources. The
LUT or register output independently drives these three outputs. Two LE outputs
drive the column or row and direct link routing connections, while one LE drives the
local interconnect resources. This allows the LUT to drive one output while the
register drives another output. This feature, called register packing, improves device
utilization because the device can use the register and the LUT for unrelated
functions. The LAB-wide synchronous load control signal is not available when using
register packing. For more information on the synchronous load control signal, refer
to
The register feedback mode allows the register output to feed back into the LUT of the
same LE to ensure that the register is packed with its own fan-out LUT, providing
another mechanism for improved fitting. The LE can also drive out registered and
unregistered versions of the LUT output.
Register Feedback
LE Carry-In
“LAB Control Signals” on page
Look-Up Table
(LUT)
shows the LEs for the Cyclone III device family.
LE Carry-Out
Register Chain
Chain
Routing from
Carry
previous LE
(DEV_CLRn)
Chip-Wide
labclkena1
labclkena2
Chapter 2: Logic Elements and Logic Array Blocks in the Cyclone III Device Family
labclr1
labclr2
Reset
labclk2
labclk1
Synchronous
LAB-Wide
Load
Asynchronous
Synchronous
Clock Enable
2–6.
Clear Logic
Clear Logic
Load and
Clock &
Select
Synchronous
LAB-Wide
Clear
Register Bypass
D
ENA
CLRN
Q
© December 2009 Altera Corporation
Register Chain
Output
Row, Column,
And Direct Link
Routing
Row, Column,
And Direct Link
Routing
Local
Routing
Logic Elements