EP3C55F484C8N Altera, EP3C55F484C8N Datasheet - Page 221

• Manufacturer Part Number: EP3C55F484C8N
• Description: IC CYCLONE III FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C55F484C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2396160
• Number Of I /o: 327
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 327
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 3491
• Family Type: Cyclone III
• No. Of I/o's: 327
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2510

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
© December 2009
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Altera Corporation
Reconfiguration
After the configuration data is successfully written into the serial configuration
device, the Cyclone III device family does not reconfigure by itself. The intelligent
host issues the PULSE_NCONFIG JTAG instruction to initialize the reconfiguration
process. During reconfiguration, the master device is reset and the SFL design no
longer exists in the Cyclone III device family and the serial configuration device
configures all the devices in the chain with your user design.
For more information about SFL, refer to
Quartus II Software.
JTAG Instructions
This section describes the instructions that are necessary for JTAG configuration for
the Cyclone III device family.
Table 9–17. JTAG Instructions
For more information about the JTAG binary instruction code, refer to the
(JTAG) Boundary-Scan Testing for Cyclone III Devices
For Cyclone III LS devices, the device can only allow mandatory JTAG 1149.1
instructions after POR. These instructions are BYPASS, SAMPLE/PRELOAD, EXTEST
and FACTORY. To enable the access of other JTAG instructions, issue the FACTORY
instruction. The FACTORY instruction puts the device in a state in which it is ready for
in-house testing and board-level testing and it must be executed before configuration
starts. When this instruction is executed, the CRAM bits content and volatile key are
cleared and the device is reset.
Notes to
(1) In Cyclone III LS devices, the CONFIG_IO, ACTIVE_DISENGAGE, PULSE_NCONFIG, and PROGRAM
(2) Use the KEY_PROG_VOL and KEY_CLR_VREG instructions for the design security feature. For more
instructions are supported, provided that the FACTORY instruction is executed. It is not necessary to execute the
FACTORY instruction prior to the JTAG configuration in Cyclone III devices because this instruction is used for
Cyclone III LS devices only.
information, refer to
Table
ACTIVE_DISENGAGE
KEY_PROG_VOL
KEY_CLR_VREG
DIS_ACTIVE_CLK
APFC_BOOT_ADDR
ACTIVE_ENGAGE
EN_ACTIVE_CLK
JTAG Instruction
FACTORY
9–17:
CONFIG_IO
“Design Security” on page
(1)
(2)
(2)
Table 9–17
9–73.
lists the supported JTAG instructions.
Cyclone III Device
AN 370: Using the Serial FlashLoader with
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chapter.
Cyclone III Device Handbook, Volume 1
Cyclone III LS Device
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IEEE 1149.1
9–61