EP2S30F484C3N Altera, EP2S30F484C3N Datasheet - Page 47
![IC STRATIX II FPGA 30K 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP2S30F484C3N
Manufacturer Part Number
EP2S30F484C3N
Description
IC STRATIX II FPGA 30K 484-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S30F484C3N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
342
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
No. Of Macrocells
33880
Family Type
Stratix II
No. Of I/o's
342
Clock Management
DLL, PLL
I/o Supply Voltage
3.6V
Operating Frequency Max
550MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1890
EP2S30F484C3N
EP2S30F484C3N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S30F484C3N
Manufacturer:
ALTERA
Quantity:
591
Part Number:
EP2S30F484C3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- Current page: 47 of 238
- Download datasheet (3Mb)
Altera Corporation
May 2007
f
See the TriMatrix Embedded Memory Blocks in Stratix II & Stratix II GX
Devices chapter in volume 2 of the Stratix II Device Handbook or the
Stratix II GX Device Handbook for more information on TriMatrix
memory.
Unit Interface Block
Table 2–4. M-RAM Row Interface Unit Signals
R0
R1
R2
R3
R4
R5
L0
L1
L2
L3
L4
L5
datain_a[14..0]
byteena_a[1..0]
datain_a[29..15]
byteena_a[3..2]
datain_a[35..30]
addressa[4..0]
addr_ena_a
clock_a
clocken_a
renwe_a
aclr_a
addressa[15..5]
datain_a[41..36]
datain_a[56..42]
byteena_a[5..4]
datain_a[71..57]
byteena_a[7..6]
datain_b[14..0]
byteena_b[1..0]
datain_b[29..15]
byteena_b[3..2]
datain_b[35..30]
addressb[4..0]
addr_ena_b
clock_b
clocken_b
renwe_b
aclr_b
addressb[15..5]
datain_b[41..36]
datain_b[56..42]
byteena_b[5..4]
datain_b[71..57]
byteena_b[7..6]
Input Signals
Stratix II Device Handbook, Volume 1
dataout_a[11..0]
dataout_a[23..12]
dataout_a[35..24]
dataout_a[47..36]
dataout_a[59..48]
dataout_a[71..60]
dataout_b[11..0]
dataout_b[23..12]
dataout_b[35..24]
dataout_b[47..36]
dataout_b[59..48]
dataout_b[71..60]
Stratix II Architecture
Output Signals
2–39
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